Issued Patents All Time
Showing 25 most recent of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12175280 | Memory transaction management | Venkatarami Mora | 2024-12-24 |
| 11663011 | System and method of VLIW instruction processing using reduced-width VLIW processor | Peter G. Sassone, Suresh K. Venkumahanti | 2023-05-30 |
| 10719325 | System and method of VLIW instruction processing using reduced-width VLIW processor | Peter G. Sassone, Suresh K. Venkumahanti | 2020-07-21 |
| 10482021 | Priority-based storage and access of compressed memory lines in memory in a processor-based system | Andres Alejandro Oportus Valenzuela, Nieyan Geng, Gurvinder Singh Chhabra, Richard Senior, Anand Janakiraman | 2019-11-19 |
| 10198362 | Reducing bandwidth consumption when performing free memory list cache maintenance in compressed memory schemes of processor-based systems | Richard Senior, Gurvinder Singh Chhabra, Andres Alejandro Oportus Valenzuela, Nieyan Geng, Raghuveer Raghavendra +2 more | 2019-02-05 |
| 10169246 | Reducing metadata size in compressed memory systems of processor-based systems | Richard Senior, Gurvinder Singh Chhabra, Andres Alejandro Oportus Valenzuela, Nieyan Geng, Raghuveer Raghavendra +2 more | 2019-01-01 |
| 10114756 | Externally programmable memory management unit | Erich James Plondke, Piyush Patel, Thomas Andrew Sartorius, Lucian Codrescu | 2018-10-30 |
| 10102031 | Bandwidth/resource management for multithreaded processors | Serag Gadelrab, Simon Peter William Booth, Aris Balatsos, Johnny Jone Wai Kuan, Myil RAMKUMAR +3 more | 2018-10-16 |
| 10061698 | Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur | Richard Senior, Gurvinder Singh Chhabra, Andres Alejandro Oportus Valenzuela, Nieyan Geng, Raghuveer Raghavendra +2 more | 2018-08-28 |
| 10025711 | Hybrid write-through/write-back cache policy managers, and related systems and methods | Peter G. Sassone, Dana Michelle Vantrease, Suresh K. Venkumahanti, Lucian Codrescu | 2018-07-17 |
| 9858201 | Selective translation lookaside buffer search and page fault | Erich James Plondke, Jiajin Tu | 2018-01-02 |
| 9824013 | Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors | Ajay Anant Ingle, Lucian Codrescu, Suresh K. Venkumahanti | 2017-11-21 |
| 9785211 | Independent power collapse methodology | Xufeng Chen, Robert A. Lester, Manojkumar Pyla, Peixin Zhong | 2017-10-10 |
| 9767025 | Write-only dataless state for maintaining cache coherency | Dana Michelle Vantrease | 2017-09-19 |
| 9678758 | Coprocessor for out-of-order loads | Lucian Codrescu, Eric W. Mahurin, Suresh K. Venkumahanti | 2017-06-13 |
| 9658793 | Adaptive mode translation lookaside buffer search and access fault | Erich James Plondke, Jiajin Tu | 2017-05-23 |
| 9606818 | Systems and methods of executing multiple hypervisors using multiple sets of processors | Erich James Plondke, Lucian Codrescu, Piyush Patel, Thomas Andrew Sartorius | 2017-03-28 |
| 9501332 | System and method to reset a lock indication | Dana Michelle Vantrease, Erich James Plondke | 2016-11-22 |
| 9239799 | Memory management unit directed access to system interfaces | Ajay Anant Ingle | 2016-01-19 |
| 9142268 | Dual-voltage domain memory buffers, and related systems and methods | Jentsung Lin, Paul Bassett, Manojkumar Pyla, Robert A. Lester | 2015-09-22 |
| 8995207 | Data storage for voltage domain crossings | Jen-Tsung Lin, Manojkumar Pyla, Martin Saint-Laurent | 2015-03-31 |
| 8943293 | Configurable cache and method to configure same | Ajay Anant Ingle, Lucian Codrescu, Jian Shen | 2015-01-27 |
| 8719503 | Configurable cache and method to configure same | Ajay Anant Ingle, Lucian Codrescu, Jian Shen | 2014-05-06 |
| 8656137 | Computer system with processor local coherency for virtualized input/output | Lucian Codrescu, Erich James Plondke, Bryan C. Bayerdorffer | 2014-02-18 |
| 8341353 | System and method to access a portion of a level two memory and a level one memory | Suresh K. Venkumahanti, Lucian Codrescu | 2012-12-25 |