Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9785601 | System and method for reducing cross coupling effects | Baker Mohammad, Martin Saint-Laurent | 2017-10-10 |
| 9384825 | Multi-port memory circuits | Jentsung Lin, Suresh K. Venkumahanti | 2016-07-05 |
| 9142268 | Dual-voltage domain memory buffers, and related systems and methods | Jentsung Lin, Manojkumar Pyla, Robert A. Lester, Christopher Edward Koob | 2015-09-22 |
| 9124276 | Sense amplifier including a level shifter | Jentsung Lin | 2015-09-01 |
| 8984217 | System and method of reducing power usage of a content addressable memory | Jian Shen, Dang D. Hoang | 2015-03-17 |
| 8884637 | Method and apparatus for testing a memory device | Baker Mohammad, Hong Sun Kim | 2014-11-11 |
| 8725991 | Register file system and method for pipelined processing | Lin Wang, Masud Kamal, Suresh K. Venkumahanti, Jian Shen | 2014-05-13 |
| 8653852 | Voltage level shifter with dynamic circuit structure having discharge delay tracking | Jentsung Lin | 2014-02-18 |
| 8627159 | Feedback scan isolation and scan bypass architecture | Paul F. Policke, Kim S. Hong | 2014-01-07 |
| 8601234 | Configurable translation lookaside buffer | Erich James Plondke, Ajay Anant Ingle, Lucian Codrescu | 2013-12-03 |
| 8527825 | Debugger based memory dump using built in self test | Hong Sun Kim, Paul F. Policke | 2013-09-03 |
| 8527804 | Architecture and method for eliminating store buffers in a DSP/processor with multiple memory accesses | Jentsung Lin, Ajay Anant Ingle, Eai-hsin A. Kuo | 2013-09-03 |
| 8522097 | Logic built-in self-test programmable pattern bit mask | Hong Sun Kim, Paul F. Policke | 2013-08-27 |
| 8466707 | Method and apparatus for testing a memory device | Baker Mohammad, Hong Sun Kim | 2013-06-18 |
| 8195916 | Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode | Ajay Anant Ingle, Sujat Jamil, Lucian Codrescu, Muhammad Ahmed | 2012-06-05 |
| 7992062 | Logic device and method supporting scan test | Martin Saint-Laurent, Prayag Bhanubhai Patel | 2011-08-02 |
| 7986165 | Voltage level shifter with dynamic circuit structure having discharge delay tracking | Jentsung Lin | 2011-07-26 |
| 7902878 | Clock gating system and method | Martin Saint-Laurent, Bassam J. Mohd | 2011-03-08 |
| 7816960 | Circuit device and method of measuring clock jitter | Martin Saint-Laurent, Boris Andreev | 2010-10-19 |
| 7746137 | Sequential circuit element including a single clocked transistor | Martin Saint-Laurent, Baker Mohammad | 2010-06-29 |
| 7724058 | Latch structure and self-adjusting pulse generator using the latch | Martin Saint-Laurent | 2010-05-25 |
| 7665003 | Method and device for testing memory | Jian Shen | 2010-02-16 |
| 7620778 | Low power microprocessor cache memory and method of operation | Baker Mohammad, Muhammad Ahmed, Sujat Jamil, Ajay Anant Ingle | 2009-11-17 |
| 7567096 | Circuit device and method of controlling a voltage swing | Baker Mohammad, Martin Saint-Laurent | 2009-07-28 |
| 7466620 | System and method for low power wordline logic for a memory | Baker Mohammad | 2008-12-16 |