Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11264976 | Symmetrically-interconnected tunable time delay circuit | Keith Alan Bowman, Nadeem N. Eleyan, Xiang Li | 2022-03-01 |
| 10068645 | Multiple cycle search content addressable memory | Kim Yaw Tong, Suresh K. Venkumahanti, Kun Ma | 2018-09-04 |
| 9837995 | Clock gating using a delay circuit | — | 2017-12-05 |
| 9208102 | Overlap checking for a translation lookaside buffer (TLB) | Suresh K. Venkumahanti, Erich James Plondke, Lucian Codrescu, Shane M. Mahon, Rahul R. Toley | 2015-12-08 |
| 8886511 | Modeling output delay of a clocked storage element(s) | — | 2014-11-11 |
| 8564354 | Circuits and methods for latch-tracking pulse generation | — | 2013-10-22 |
| 8432195 | Latch circuits with synchronous data loading and self-timed asynchronous data capture | David Paul Hoff | 2013-04-30 |
| 8314643 | Circuits and methods employing a local power block for leakage reduction | Anthony D. Klein | 2012-11-20 |
| 7725792 | Dual-path, multimode sequential storage element | Manish Garg | 2010-05-25 |
| 7301384 | Multimode, uniform-latency clock generation circuit | Jeffrey Herbert Fischer, William Goodall, III | 2007-11-27 |
| 7279935 | Method and apparatus for reducing clock enable setup time in a multi-enabled clock gating circuit | Jeffrey Herbert Fischer, William Goodall, III | 2007-10-09 |
| 6788077 | Automated test sequence editor and engine for transformer testing | — | 2004-09-07 |