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Multiple cycle search content addressable memory |
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Clock gating using a delay circuit |
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Overlap checking for a translation lookaside buffer (TLB) |
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Modeling output delay of a clocked storage element(s) |
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Circuits and methods for latch-tracking pulse generation |
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Dual-path, multimode sequential storage element |
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Multimode, uniform-latency clock generation circuit |
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Automated test sequence editor and engine for transformer testing |
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2004-09-07 |