Issued Patents All Time
Showing 25 most recent of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9804969 | Speculative addressing using a virtual address-to-physical address page crossing buffer | Suresh K. Venkumahanti, Jiajin Tu | 2017-10-31 |
| 9122486 | Bimodal branch predictor encoded in a branch instruction | Suresh K. Venkumahanti, Lucian Codrescu, Stephen Robert Shannon, Lin Wang, Daisy T. Palal +1 more | 2015-09-01 |
| 8078818 | Method and system for migrating memory segments | William J. Walker, Paras A. Shah, James Yu, Kenneth A. Jansen, Vasileios Balabanos +1 more | 2011-12-13 |
| 7827356 | System and method of using an N-way cache | Suresh K. Venkumahanti | 2010-11-02 |
| 7685411 | Multi-mode instruction memory unit | Muhammad Ahmed, Lucian Codrescu, Erich James Plondke, William C. Anderson, Robert A. Lester | 2010-03-23 |
| 7502895 | Techniques for reducing castouts in a snoop filter | Kourosh Gharachorloo | 2009-03-10 |
| 7120758 | Technique for improving processor performance | Robert A. Lester, Jens K. Ramsey, William J. Walker, John E. Larson, James R. Andre +1 more | 2006-10-10 |
| 6961800 | Method for improving processor performance | Robert A. Lester, Kenneth T. Chin, Jim Blocker, John E. Larson, Paul B. Rawlins | 2005-11-01 |
| 6865647 | Dynamic cache partitioning | Sompong Paul Olarig, John E. Jenne | 2005-03-08 |
| 6848015 | Arbitration technique based on processor task priority | — | 2005-01-25 |
| 6829665 | Next snoop predictor in a host controller | Paul B. Rawlins, Kenneth T. Chin | 2004-12-07 |
| 6823409 | Coherency control module for maintaining cache coherency in a multi-processor-bus system | Paul B. Rawlins | 2004-11-23 |
| 6662272 | Dynamic cache partitioning | Sompong Paul Olarig, John E. Jenne | 2003-12-09 |
| 6505260 | Computer system with adaptive memory arbitration scheme | Kenneth T. Chin, C. Kevin Coffee, Michael J. Collins, Jerome J. Johnson, Robert A. Lester +2 more | 2003-01-07 |
| 6470429 | System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops | Robert A. Lester | 2002-10-22 |
| 6463510 | Apparatus for identifying memory requests originating on remote I/O devices as noncacheable | Robert L. Woods | 2002-10-08 |
| 6356972 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Robert A. Lester +1 more | 2002-03-12 |
| 6286083 | Computer system with adaptive memory arbitration scheme | Kenneth T. Chin, Jerome J. Johnson, Robert A. Lester, Gary J. Piccirillo, Jeffrey C. Stevens +2 more | 2001-09-04 |
| 6279065 | Computer system with improved memory access | Kenneth T. Chin, Jerome J. Johnson, Robert A. Lester, Gary J. Piccirillo, C. Kevin Coffee +1 more | 2001-08-21 |
| 6272580 | Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration system | Jeff Stevens, Robert A. Lester, Jeff W. Wolford, Peter Bow Kwong Lee | 2001-08-07 |
| 6272651 | System and method for improving processor read latency in a system employing error checking and correction | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Robert A. Lester +1 more | 2001-08-07 |
| 6269433 | Memory controller using queue look-ahead to reduce memory latency | Gary J. Piccirillo | 2001-07-31 |
| 6249847 | Computer system with synchronous memory arbiter that permits asynchronous memory requests | Kenneth T. Chin, Robert A. Lester, Gary J. Piccirillo, Michael J. Collins | 2001-06-19 |
| 6247102 | Computer system employing memory controller and bridge interface permitting concurrent operation | Kenneth T. Chin, Jerome J. Johnson, Robert A. Lester, Gary J. Piccirillo, Jeffrey C. Stevens +3 more | 2001-06-12 |
| 6233661 | Computer system with memory controller that hides the next cycle during the current cycle | Gary J. Piccirillo | 2001-05-15 |