Issued Patents All Time
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10956342 | Variable channel multi-controller memory system | John M. MacLaren, Landon Laws, Anne Hughes | 2021-03-23 |
| 10719058 | System and method for memory control having selectively distributed power-on processing | John M. MacLaren, Sreenivasan Kandagatla | 2020-07-21 |
| 10275306 | System and method for memory control having adaptively split addressing of error-protected data words in memory transactions for inline storage configurations | John M. MacLaren, Carl Nels Olson, Thomas J. Shepherd | 2019-04-30 |
| 7320086 | Error indication in a raid memory system | Tim Majni, Gary J. Piccirillo, John M. MacLaren, Robert A. Lester, John E. Larson +8 more | 2008-01-15 |
| 7194577 | Memory latency and bandwidth optimizations | Benjamin H. Clark, Gary J. Piccirillo, John M. MacLaren | 2007-03-20 |
| 7028213 | Error indication in a raid memory system | Tim Majni, Gary J. Piccirillo, John M. MacLaren, Robert A. Lester, John E. Larson +8 more | 2006-04-11 |
| 7010652 | Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency | Gary J. Piccirillo, John M. MacLaren, Robert A. Lester, John E. Larson, Benjamin H. Clark | 2006-03-07 |
| 6981095 | Hot replace power control sequence logic | John M. MacLaren, Robert A. Lester, Gary J. Piccirillo, John E. Larson, Christian Post +3 more | 2005-12-27 |
| 6938133 | Memory latency and bandwidth optimizations | Benjamin H. Clark, Gary J. Piccirillo, John M. MacLaren | 2005-08-30 |
| 6892271 | Memory module resync | Gary J. Piccirillo, John E. Larson | 2005-05-10 |
| 6854070 | Hot-upgrade/hot-add memory | John M. MacLaren, Robert A. Lester, John E. Larson, Gary J. Piccirillo, Christian Post +4 more | 2005-02-08 |
| 6832286 | Memory auto-precharge | Benjamin H. Clark, Gary J. Piccirillo, John M. MacLaren | 2004-12-14 |
| 6832340 | Real-time hardware memory scrubbing | John E. Larson, John M. MacLaren, Robert A. Lester, Gary J. Piccirillo, Patrick L. Ferguson | 2004-12-14 |
| 6785785 | Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrency | Gary J. Piccirillo, John M. MacLaren, Robert A. Lester, John E. Larson, Benjamin H. Clark | 2004-08-31 |
| 6785835 | Raid memory | John M. MacLaren, Paul Santeler, Kenneth A. Jansen, Sompong Paul Olarig, Robert A. Lester +3 more | 2004-08-31 |
| 6766469 | Hot-replace of memory | John E. Larson, John M. MacLaren, Gary J. Piccirillo, Robert A. Lester, Christian Post +4 more | 2004-07-20 |
| 6684292 | Memory module resync | Gary J. Piccirillo, John E. Larson | 2004-01-27 |
| 6640282 | Hot replace power control sequence logic | John M. MacLaren, Robert A. Lester, Gary J. Piccirillo, John E. Larson, Christian Post +3 more | 2003-10-28 |
| 6505260 | Computer system with adaptive memory arbitration scheme | Kenneth T. Chin, C. Kevin Coffee, Michael J. Collins, Phillip M. Jones, Robert A. Lester +2 more | 2003-01-07 |
| 6356972 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Phillip M. Jones, Robert A. Lester +1 more | 2002-03-12 |
| 6286083 | Computer system with adaptive memory arbitration scheme | Kenneth T. Chin, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo, Jeffrey C. Stevens +2 more | 2001-09-04 |
| 6279065 | Computer system with improved memory access | Kenneth T. Chin, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo, C. Kevin Coffee +1 more | 2001-08-21 |
| 6272651 | System and method for improving processor read latency in a system employing error checking and correction | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Phillip M. Jones, Robert A. Lester +1 more | 2001-08-07 |
| 6247102 | Computer system employing memory controller and bridge interface permitting concurrent operation | Kenneth T. Chin, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo, Jeffrey C. Stevens +3 more | 2001-06-12 |
| 6216190 | System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Phillip M. Jones, Robert A. Lester +1 more | 2001-04-10 |