JS

Jeffrey C. Stevens

CC Compaq Computer: 17 patents #27 of 1,604Top 2%
HP HP: 6 patents #2,518 of 16,619Top 20%
CG Compaq Information Technologies Group: 1 patents #84 of 407Top 25%
Overall (All Time): #171,499 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11720154 Environmental and temperature based computing device fan adjustments — 2023-08-08
11507177 Power management systems Robert C. Brooks, Michael R. Durham, Mark A. Piwonka, Nam H. Nguyen 2022-11-22
10691207 Display devices with virtual reprsentations of electronic devices Kent E. Biggs, Robert Paul Martin, Charles J. Stancil, Harold Merkel 2020-06-23
10248178 Power consumption limit associated with power over ethernet (POE) computing system Robert C. Brooks, Patrick L. Ferguson, Charles N. Shaver 2019-04-02
9639135 Power consumption limit associated with power over ethernet (PoE) computing system Robert C. Brooks, Patrick L. Ferguson, Charles N. Shaver 2017-05-02
6601168 Computer fan speed system to reduce audible perceptibility of fan speed changes Charles J. Stancil 2003-07-29
6505260 Computer system with adaptive memory arbitration scheme Kenneth T. Chin, C. Kevin Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones +2 more 2003-01-07
6286083 Computer system with adaptive memory arbitration scheme Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo +2 more 2001-09-04
6247102 Computer system employing memory controller and bridge interface permitting concurrent operation Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo +3 more 2001-06-12
6226700 Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices Shaun Wandler, Jeff W. Wolford, Robert L. Woods, Danny Higby, Russ Wunderlich +2 more 2001-05-01
6101566 Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices Robert L. Woods, Jeff W. Wolford, Shaun Wandler, Todd Deschepper, Jeffrey Wilson +2 more 2000-08-08
6088517 Interfacing direct memory access devices to a non-ISA bus Christopher C. Wanner, Robert A. Lester, Dwight D. Riley, David J. Maguire, James R. Edwards 2000-07-11
6041401 Computer system that places a cache memory into low power mode in response to special bus cycles executed on the bus Jens K. Ramsey, Michael E. Tubbs, Charles J. Stancil 2000-03-21
5813022 Circuit for placing a cache memory into low power mode in response to special bus cycles executed on the bus Jens K. Ramsey, Michael E. Tubbs, Charles J. Stancil 1998-09-22
5793693 Cache memory using unique burst counter circuitry and asynchronous interleaved RAM banks for zero wait state operation Michael J. Collins, Guy E. McSwain 1998-08-11
5781925 Method of preventing cache corruption during microprocessor pipelined burst operations John E. Larson, Jens K. Ramsey, Michael J. Collins 1998-07-14
5778413 Programmable memory controller having two level look-up for memory timing parameter John E. Larson, Gary W. Thome, Michael J. Collins, Michael Moriarty 1998-07-07
5774680 Interfacing direct memory access devices to a non-ISA bus Christopher C. Wanner, Robert A. Lester, Dwight D. Riley, David J. Maguire, James R. Edwards 1998-06-30
5724550 Using an address pin as a snoop invalidate signal during snoop cycles — 1998-03-03
5617557 Using an address pin as a snoop invalidate signal during snoop cycles — 1997-04-01
5446863 Cache snoop latency prevention apparatus Jens K. Ramsey, Randy M. Bonella, Philip C. Kelly 1995-08-29
5426765 Multiprocessor cache abitration Mike Jackson, Roger E. Tipley, Jens K. Ramsey, Sompong Paul Olarig, Philip C. Kelly 1995-06-20
5335335 Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed Mike Jackson, Roger E. Tipley 1994-08-02
5325503 Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line Jens K. Ramsey, Randy M. Bonella, Philip C. Kelly 1994-06-28