Issued Patents All Time
Showing 25 most recent of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11100000 | Embedded image management | Aland B. Adams, Michael S. Bunker, John Sarni | 2021-08-24 |
| 9003091 | Flow control for a Serial Peripheral Interface bus | David F. Heinrich, Theodore F. Emerson, Kevin B. Leigh, Vincent Nguyen, Andrew Brown | 2015-04-07 |
| 6215504 | Line drawing using operand routing and operation selective multimedia extension unit | Brian E. Longhenry, John S. Thayer | 2001-04-10 |
| 6154831 | Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values | John S. Thayer, John G. Favor, Frederick Daniel Weber | 2000-11-28 |
| 6115791 | Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control | Michael J. Collins | 2000-09-05 |
| 6061521 | Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle | John S. Thayer, John G. Favor, Frederick Daniel Weber | 2000-05-09 |
| 6009505 | System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot | John S. Thayer, Brian E. Longhenry, John G. Favor, Frederick Daniel Weber | 1999-12-28 |
| 5991865 | MPEG motion compensation using operand routing and performing add and divide in a single instruction | Brian E. Longhenry, John S. Thayer | 1999-11-23 |
| 5960459 | Memory controller having precharge prediction based on processor and PCI bus cycles | Michael Moriarty, John E. Larson | 1999-09-28 |
| 5938739 | Memory controller including write posting queues, bus read control logic, and a data contents counter | Michael J. Collins, Michael Moriarty, Jens K. Ramsey, John E. Larson | 1999-08-17 |
| 5931892 | Enhanced adaptive filtering technique | John S. Thayer | 1999-08-03 |
| 5918023 | System design to support either Pentium Pro processors, Pentium II processors, and future processor without having to replace the system board | Earl C. Reeves, David Olson, Kameron Ayati | 1999-06-29 |
| 5892964 | Computer bridge interfaces for accelerated graphics port and peripheral component interconnect devices | Ronald T. Horan, Sompong Paul Olarig | 1999-04-06 |
| 5893145 | System and method for routing operands within partitions of a source register to partitions within a destination register | John S. Thayer, Brian E. Longhenry | 1999-04-06 |
| 5862063 | Enhanced wavetable processing technique on a vector processor having operand routing and slot selectable operations | John S. Thayer | 1999-01-19 |
| 5857116 | Circuit for disabling an address masking control signal when a microprocessor is in a system management mode | Basem Abu Ayash | 1999-01-05 |
| 5848267 | Computer system speed control using memory refresh counter | — | 1998-12-08 |
| 5822756 | Microprocessor cache memory way prediction based on the way of a previous memory read | Jens K. Ramsey | 1998-10-13 |
| 5819105 | System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device | Michael Moriarty, Michael J. Collins, John E. Larson | 1998-10-06 |
| 5813038 | Memory controller having precharge prediction based on processor and PC bus cycles | Michael Moriarty, John E. Larson | 1998-09-22 |
| 5809549 | Burst SRAMs for use with a high speed clock | Michael J. Collins | 1998-09-15 |
| 5778433 | Computer system including a first level write-back cache and a second level cache | Michael J. Collins | 1998-07-07 |
| 5778413 | Programmable memory controller having two level look-up for memory timing parameter | Jeffrey C. Stevens, John E. Larson, Michael J. Collins, Michael Moriarty | 1998-07-07 |
| 5692154 | Circuit for masking a dirty status indication provided by a cache dirty memory under certain conditions so that a cache memory controller properly controls a cache tag memory | Brian B. Tucker | 1997-11-25 |
| 5664225 | Circuit for disabling an address masking control signal when a microprocessor is in a system management mode | Basem Abu Ayash | 1997-09-02 |