Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6298438 | System and method for conditional moving an operand from a source register to destination register | John G. Favor, Frederick Daniel Weber | 2001-10-02 |
| 6215504 | Line drawing using operand routing and operation selective multimedia extension unit | Brian E. Longhenry, Gary W. Thome | 2001-04-10 |
| 6173366 | Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage | John G. Favor, Frederick Daniel Weber | 2001-01-09 |
| 6154831 | Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values | Gary W. Thome, John G. Favor, Frederick Daniel Weber | 2000-11-28 |
| 6141673 | Microprocessor modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instructions | John G. Favor, Frederick Daniel Weber | 2000-10-31 |
| 6061521 | Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle | Gary W. Thome, John G. Favor, Frederick Daniel Weber | 2000-05-09 |
| 6047372 | Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot | Brian E. Longhenry, John G. Favor, Frederick Daniel Weber | 2000-04-04 |
| 6009505 | System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot | Gary W. Thome, Brian E. Longhenry, John G. Favor, Frederick Daniel Weber | 1999-12-28 |
| 6006245 | Enhanced fast fourier transform technique on vector processor with operand routing and slot-selectable operation | — | 1999-12-21 |
| 5991865 | MPEG motion compensation using operand routing and performing add and divide in a single instruction | Brian E. Longhenry, Gary W. Thome | 1999-11-23 |
| 5941938 | System and method for performing an accumulate operation on one or more operands within a partitioned register | — | 1999-08-24 |
| 5931892 | Enhanced adaptive filtering technique | Gary W. Thome | 1999-08-03 |
| 5909572 | System and method for conditionally moving an operand from a source register to a destination register | John G. Favor, Frederick Daniel Weber | 1999-06-01 |
| 5893145 | System and method for routing operands within partitions of a source register to partitions within a destination register | Gary W. Thome, Brian E. Longhenry | 1999-04-06 |
| 5862063 | Enhanced wavetable processing technique on a vector processor having operand routing and slot selectable operations | Gary W. Thome | 1999-01-19 |
| 5850227 | Bit map stretching using operand routing and operation selective multimedia extension unit | Brian E. Longhenry | 1998-12-15 |
| 5812876 | DMA controller which can be controlled by host and local processors | Mark W. Welker | 1998-09-22 |
| 5801975 | Computer modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instruction cycles | John G. Favor, Frederick Daniel Weber | 1998-09-01 |
| 5598579 | System fpr transferring data between two buses using control registers writable by host processor connected to system bus and local processor coupled to local bus | Mark W. Welker | 1997-01-28 |
| 5590378 | Apparatus for aligning and padding data on transfers between devices of different data widths and organizations | Patrick L. Ferguson | 1996-12-31 |
| 5517646 | Expansion device configuration system having two configuration modes which uses automatic expansion configuration sequence during first mode and configures the device individually during second mode | Gary J. Piccirillo, Mark W. Welker | 1996-05-14 |
| 5381530 | Programmable logic system for filtering commands to a microprocessor | Montgomery C. McGraw | 1995-01-10 |
| 5341494 | Memory accessing system with an interface and memory selection unit utilizing write protect and strobe signals | Dale J. Mayer, Javier F. Izquierdo, Paul R. Culley, John A. Landry | 1994-08-23 |
| 5241681 | Computer system having an internal cach microprocessor slowdown circuit providing an external address signal | Mustafa A. Hamid, Roy E. Thoma, III | 1993-08-31 |
| 5226122 | Programmable logic system for filtering commands to a microprocessor | Montgomery C. McGraw | 1993-07-06 |