Issued Patents All Time
Showing 1–25 of 166 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393426 | Store-to-load forwarding correctness checks at store instruction commit | Srivatsan Srinivasan | 2025-08-19 |
| 12332793 | Unforwardable load instruction re-execution eligibility based on cache update by identified store instruction | Srivatsan Srinivasan | 2025-06-17 |
| 12299449 | Performance and power efficient processor when switching between fetching from decoded and non-decoded instruction sources | Michael N. Michael | 2025-05-13 |
| 12282430 | Macro-op cache data entry pointers distributed as initial pointers held in tag array and next pointers held in data array for efficient and performant variable length macro-op cache entries | Michael N. Michael | 2025-04-22 |
| 12253951 | Microprocessor with branch target buffer whose entries include fetch block hotness counters used for selective filtering of macro-op cache allocations | Michael N. Michael | 2025-03-18 |
| 12229252 | Microprocessor that prevents store-to-load forwarding between different translation contexts | — | 2025-02-18 |
| 12182019 | Microprocessor that prevents same address load-load ordering violations using physical address proxies | Srivatsan Srinivasan | 2024-12-31 |
| 12118076 | Physically-tagged data cache memory that uses translation context to reduce likelihood that entries allocated during execution under one translation context are accessible during execution under another translation context | Srivatsan Srinivasan | 2024-10-15 |
| 12118360 | Branch target buffer miss handling | Michael N. Michael | 2024-10-15 |
| 12117937 | Using physical address proxies to handle synonyms when writing store data to a virtually-indexed cache | Srivatsan Srinivasan, Robert Haskell Utley | 2024-10-15 |
| 12106111 | Prediction unit with first predictor that provides a hashed fetch address of a current fetch block to its own input and to a second predictor that uses it to predict the fetch address of a next fetch block | Michael N. Michael | 2024-10-01 |
| 12099448 | Virtually-indexed cache coherency using physical address proxies | Srivatsan Srinivasan, Robert Haskell Utley | 2024-09-24 |
| 12093179 | Store-to-load forwarding correctness checks using physical address proxies stored in load queue entries | Srivatsan Srinivasan | 2024-09-17 |
| 12086245 | Processor that prevents speculative execution across translation context change boundaries to mitigate side channel attacks | David S. Oliver | 2024-09-10 |
| 12086063 | Physical address proxy reuse management | Srivatsan Srinivasan, Robert Haskell Utley | 2024-09-10 |
| 12079129 | Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries | Srivatsan Srinivasan | 2024-09-03 |
| 12079126 | Unforwardable load instruction re-execution eligibility based on cache update by identified store instruction | Srivatsan Srinivasan | 2024-09-03 |
| 12073220 | Store-to-load forwarding correctness checks at store instruction commit | Srivatsan Srinivasan | 2024-08-27 |
| 12061555 | Non-cacheable access handling in processor with virtually-tagged virtually-indexed data cache | Srivatsan Srinivasan | 2024-08-13 |
| 12020032 | Prediction unit that provides a fetch block descriptor each clock cycle | Michael N. Michael | 2024-06-25 |
| 12014180 | Dynamically foldable and unfoldable instruction fetch pipeline | Michael N. Michael, Vihar Soneji | 2024-06-18 |
| 12014178 | Folded instruction fetch pipeline | Michael N. Michael, Vihar Soneji | 2024-06-18 |
| 12008375 | Branch target buffer that stores predicted set index and predicted way number of instruction cache | Michael N. Michael, Vihar Soneji | 2024-06-11 |
| 12001843 | Microprocessor including a decode unit that performs pre-execution of load constant micro-operations | David S. Oliver | 2024-06-04 |
| 11989286 | Conditioning store-to-load forwarding (STLF) on past observations of STLF propriety | Srivatsan Srinivasan | 2024-05-21 |