Issued Patents All Time
Showing 51–75 of 166 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11397686 | Store-to-load forwarding using physical address proxies to identify candidate set of store queue entries | Srivatsan Srinivasan | 2022-07-26 |
| 11386016 | Flexible storage and optimized search for multiple page sizes in a translation lookaside buffer | George Van Horn Leming, III, Stephan Jourdan, Jonathan Christopher Perry, Bret L. Toll | 2022-07-12 |
| 10372615 | Data management for cache memory | Kjeld Svendsen | 2019-08-06 |
| 10348281 | Clock control based on voltage associated with a microprocessor | David S. Oliver, Matthew William Ashcraft, Luca Ravezzi, Alfred Yeung | 2019-07-09 |
| 9798672 | Data managment for cache memory | Kjeld Svendsen | 2017-10-24 |
| 9280479 | Multi-level store merging in a cache and memory hierarchy | David A. Kruckemyer, Matthew William Ashcraft | 2016-03-08 |
| 9213643 | Broadcast messaging and acknowledgment messaging for power management in a multiprocessor system | David A. Kruckemyer | 2015-12-15 |
| 9058284 | Method and apparatus for performing table lookup | Amos Ben-Meir | 2015-06-16 |
| 8949581 | Threshold controlled limited out of order load execution | Matthew William Ashcraft | 2015-02-03 |
| 8850121 | Outstanding load miss buffer with shared entries | Matthew William Ashcraft, David A. Kruckemyer | 2014-09-30 |
| 8806135 | Load store unit with load miss result buffer | Matthew William Ashcraft, David A. Kruckemyer | 2014-08-12 |
| 8793435 | Load miss result buffer with shared data lines | Matthew William Ashcraft, David A. Kruckemyer | 2014-07-29 |
| 8656139 | Digital processor for processing long and short pointers and converting each between a common format | Stephan G. Meier, Evan Gewirtz, Robert Hathaway, Eric M. Trehus | 2014-02-18 |
| 8543843 | Virtual core management | Yu Qing Cheng, Peter N. Glaskowsky, Carlos Puchol, Seungyoon Peter Song | 2013-09-24 |
| 8499293 | Symbolic renaming optimization of a trace | Matthew William Ashcraft, Christopher Patrick Nelson, Ivan Pavle Radivojevic, Joseph B. Rowlands, Richard Win Thaik | 2013-07-30 |
| 8370609 | Data cache rollbacks for failed speculative traces with memory operations | Paul G. Chan, Graham Ricketson Murphy, Joseph B. Rowlands | 2013-02-05 |
| 8370576 | Cache rollback acceleration via a bank based versioning cache ciruit | Paul G. Chan, Graham Ricketson Murphy, Joseph B. Rowlands | 2013-02-05 |
| 8281308 | Virtual core remapping based on temperature | Yu Qing Cheng, Peter N. Glaskowsky, Carlos Puchol, Seungyoon Peter Song | 2012-10-02 |
| 8225315 | Virtual core management | Yu Qing Cheng, Peter N. Glaskowsky, Laurent Moll, Carlos Puchol, Joseph B. Rowlands +1 more | 2012-07-17 |
| 8051247 | Trace based deallocation of entries in a versioning cache circuit | Paul G. Chan, Graham Ricketson Murphy, Joseph B. Rowlands | 2011-11-01 |
| 8037285 | Trace unit | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar, Matthew William Ashcraft, Ivan Pavle Radivojevic | 2011-10-11 |
| 8032710 | System and method for ensuring coherency in trace execution | Matthew William Ashcraft, Joseph B. Rowlands, Leonard Eric Shar, Richard Win Thaik | 2011-10-04 |
| 8024522 | Memory ordering queue/versioning cache circuit | Paul G. Chan, Graham Ricketson Murphy, Joseph B. Rowlands | 2011-09-20 |
| 8019944 | Checking for a memory ordering violation after a speculative cache write | Paul G. Chan, Graham Ricketson Murphy, Joseph B. Rowlands | 2011-09-13 |
| 8015359 | Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit | Joseph B. Rowlands, Leonard Eric Shar, Richard Win Thaik | 2011-09-06 |