Issued Patents All Time
Showing 25 most recent of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12332309 | Built-in self-test for network on chip fabric | Dawn Maxon, Eric Norige, Joji Philip, William John Bainbridge | 2025-06-17 |
| 11144457 | Enhanced page locality in network-on-chip (NoC) architectures | Joji Philip | 2021-10-12 |
| 10983910 | Bandwidth weighting mechanism based network-on-chip (NoC) configuration | Joji Philip | 2021-04-20 |
| 10749811 | Interface virtualization and fast path for Network on Chip | Joji Philip, Sailesh Kumar, Nishant Rao | 2020-08-18 |
| 10735335 | Interface virtualization and fast path for network on chip | Joji Philip, Sailesh Kumar, Nishant Rao | 2020-08-04 |
| 10027433 | Multiple clock domains in NoC | Joji Philip, Sailesh Kumar | 2018-07-17 |
| 9781043 | Identification of internal dependencies within system components for evaluating potential protocol level deadlocks | Sailesh Kumar, Eric Norige, Joji Philip | 2017-10-03 |
| 9774498 | Hierarchical asymmetric mesh with virtual routers | Sailesh Kumar, Eric Norige, Joji Philip, Mahmud-Ul Hassan, Sundari Mitra | 2017-09-26 |
| 9563562 | Page crossing prefetches | Anurag Chaudhary | 2017-02-07 |
| 9253085 | Hierarchical asymmetric mesh with virtual routers | Sailesh Kumar, Eric Norige, Joji Philip, Mahmud-Ul Hassan, Sundari Mitra | 2016-02-02 |
| 9185026 | Tagging and synchronization for fairness in NOC interconnects | Sailesh Kumar, Eric Norige, Joji Philip, Mahmud-Ul Hassan, Sundari Mitra | 2015-11-10 |
| 9130856 | Creating multiple NoC layers for isolation or avoiding NoC traffic congestion | Sailesh Kumar, Eric Norige, Joji Philip, Mahmud-Ul Hassan, Sundari Mitra | 2015-09-08 |
| 9009648 | Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification | Sailesh Kumar, Eric Norige, Joji Philip, Mahmud-Ul Hassan, Sundari Mitra | 2015-04-14 |
| 9007920 | QoS in heterogeneous NoC by assigning weights to NoC node channels and using weighted arbitration at NoC nodes | Sailesh Kumar, Eric Norige, Joji Philip, Mahmud-Ul Hassan, Sundari Mitra | 2015-04-14 |
| 8499293 | Symbolic renaming optimization of a trace | Matthew William Ashcraft, John G. Favor, Christopher Patrick Nelson, Ivan Pavle Radivojevic, Richard Win Thaik | 2013-07-30 |
| 8370609 | Data cache rollbacks for failed speculative traces with memory operations | John G. Favor, Paul G. Chan, Graham Ricketson Murphy | 2013-02-05 |
| 8370576 | Cache rollback acceleration via a bank based versioning cache ciruit | John G. Favor, Paul G. Chan, Graham Ricketson Murphy | 2013-02-05 |
| 8225315 | Virtual core management | Yu Qing Cheng, John G. Favor, Peter N. Glaskowsky, Laurent Moll, Carlos Puchol +1 more | 2012-07-17 |
| 8051247 | Trace based deallocation of entries in a versioning cache circuit | John G. Favor, Paul G. Chan, Graham Ricketson Murphy | 2011-11-01 |
| 8037285 | Trace unit | Richard Win Thaik, John G. Favor, Leonard Eric Shar, Matthew William Ashcraft, Ivan Pavle Radivojevic | 2011-10-11 |
| 8032710 | System and method for ensuring coherency in trace execution | Matthew William Ashcraft, John G. Favor, Leonard Eric Shar, Richard Win Thaik | 2011-10-04 |
| 8024522 | Memory ordering queue/versioning cache circuit | John G. Favor, Paul G. Chan, Graham Ricketson Murphy | 2011-09-20 |
| 8019944 | Checking for a memory ordering violation after a speculative cache write | John G. Favor, Paul G. Chan, Graham Ricketson Murphy | 2011-09-13 |
| 8015359 | Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit | John G. Favor, Leonard Eric Shar, Richard Win Thaik | 2011-09-06 |
| 8010745 | Rolling back a speculative update of a non-modifiable cache line | John G. Favor, Paul G. Chan, Graham Ricketson Murphy | 2011-08-30 |