Issued Patents All Time
Showing 25 most recent of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12230347 | System and memory with configurable metadata portion | Jungwon Suh, Dexter Tamio Chun, Anand Srinivasan, Olivier Alavoine | 2025-02-18 |
| 11728003 | System and memory with configurable error-correction code (ECC) data protection and related methods | Jungwon Suh, Dexter Tamio Chun, Anand Srinivasan, Olivier Alavoine | 2023-08-15 |
| 11520706 | Dram-aware caching | Alain Artieri, Rakesh Gupta, Subbarao Palacharla, Kedar Bhole, Carlo Spitale +8 more | 2022-12-06 |
| 11372717 | Memory with system ECC | Jungwon Suh, Michael Hawjing Lo, Dexter Tamio Chun, Xavier Leloup | 2022-06-28 |
| 11295803 | Memory with dynamic voltage scaling | Jungwon Suh, Michael Hawjing Lo, Dexter Tamio Chun, Xavier Leloup | 2022-04-05 |
| 9852081 | STLB prefetching for a multi-dimension engine | — | 2017-12-26 |
| 9760498 | Hybrid cache comprising coherent and non-coherent lines | — | 2017-09-12 |
| 9734070 | System and method for a shared cache with adaptive partitioning | Alain Artieri, Subbarao Palacharla, Raghu Sankuratri, Kedar Bhole, Vinod Chamarty | 2017-08-15 |
| 9639469 | Coherency controller with reduced data buffer | Jean-Jacques Lecler, Jonah Proujansky-Bell | 2017-05-02 |
| 9563560 | Adaptive tuning of snoops | Jean-Jacques Lecler | 2017-02-07 |
| 9465749 | DMA engine with STLB prefetch capabilities and tethered prefetching | Jean-Jacques Lecler, Philippe Boucard | 2016-10-11 |
| 9396130 | System translation look-aside buffer integrated in an interconnect | Philippe Boucard, Jean-Jacques Lecler | 2016-07-19 |
| 9170949 | Simplified controller with partial coherency | — | 2015-10-27 |
| 9141556 | System translation look-aside buffer with request-based allocation and prefetching | Jean-Jacques Lecler, Philippe Boucard | 2015-09-22 |
| 9104423 | Method and system for advance wakeup from low-power sleep states | Sagheer Ahmad, Jay Kishora Gupta | 2015-08-11 |
| 9104421 | Training, power-gating, and dynamic frequency changing of a memory controller | Sagheer Ahmad, Edward L. Riegelsberger, Tony Yuhsiang Cheng, Brian K. Langendorf | 2015-08-11 |
| 8930638 | Method and apparatus for supporting target-side security in a cache coherent system | Jean-Jacques Lecler, Philippe Boucard | 2015-01-06 |
| 8788737 | Transport of PCI-ordered traffic over independent networks | Philippe Boucard, Jean-Jacques Lecler, Philippe Martin | 2014-07-22 |
| 8225315 | Virtual core management | Yu Qing Cheng, John G. Favor, Peter N. Glaskowsky, Carlos Puchol, Joseph B. Rowlands +1 more | 2012-07-17 |
| 8208470 | Connectionless packet data transport over a connection-based point-to-point link | Manu Gulati, Barton Sano | 2012-06-26 |
| 8176229 | Hypertransport/SPI-4 interface supporting configurable deskewing | Manu Gulati | 2012-05-08 |
| 7958312 | Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state | Yu Qing Cheng, Peter N. Glaskowsky, Seungyoon Peter Song | 2011-06-07 |
| 7934054 | Re-fetching cache memory enabling alternative operational modes | Peter N. Glaskowsky, Joseph B. Rowlands | 2011-04-26 |
| 7904659 | Power conservation via DRAM access reduction | Yu Qing Cheng, Peter N. Glaskowsky, Seungyoon Peter Song | 2011-03-08 |
| 7899990 | Power conservation via DRAM access | Seungyoon Peter Song, Peter N. Glaskowsky, Yu Qing Cheng | 2011-03-01 |