Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12332811 | Method and apparatus for exclusive access fairness in memory systems with distributed exclusive access management | Ameline Le Rouzic, Nordine Chaibelaine, Olivier Loison | 2025-06-17 |
| 11940939 | Encoding byte information on a data bus with separate code | Christophe J. Layer, Luc Montperrus | 2024-03-26 |
| 10606339 | Coherent interconnect power reduction using hardware controlled split snoop directories | Christophe Avoinne, Luc Montperrus, Rakesh Gupta | 2020-03-31 |
| 9882839 | Zero-latency network on chip (NoC) | Jean-Jacques Lecler | 2018-01-30 |
| 9608935 | Tunneling within a network-on-chip topology | Philippe Martin | 2017-03-28 |
| 9471538 | Network on a chip socket protocol | Jean-Jacques Lecler, Boris Boutillier | 2016-10-18 |
| 9465749 | DMA engine with STLB prefetch capabilities and tethered prefetching | Laurent Moll, Jean-Jacques Lecler | 2016-10-11 |
| 9396130 | System translation look-aside buffer integrated in an interconnect | Jean-Jacques Lecler, Laurent Moll | 2016-07-19 |
| 9225665 | Network on a chip socket protocol | Jean-Jacques Lecler, Boris Boutillier | 2015-12-29 |
| 9177615 | Power disconnect unit for use in data transport topology of network on chip design having asynchronous clock domain adapter sender and receiver each at a separate power domain | — | 2015-11-03 |
| 9172656 | Method and device for managing priority during the transmission of a message | Cesar Douady | 2015-10-27 |
| 9141556 | System translation look-aside buffer with request-based allocation and prefetching | Laurent Moll, Jean-Jacques Lecler | 2015-09-22 |
| 9069912 | System and method of distributed initiator-local reorder buffers | Jean-Jacques Lecler | 2015-06-30 |
| 9049124 | Zero-latency network on chip (NoC) | Jean-Jacques Lecler | 2015-06-02 |
| 8930638 | Method and apparatus for supporting target-side security in a cache coherent system | Laurent Moll, Jean-Jacques Lecler | 2015-01-06 |
| 8824295 | Link between chips using virtual channels and credit based flow control | — | 2014-09-02 |
| 8788737 | Transport of PCI-ordered traffic over independent networks | Jean-Jacques Lecler, Philippe Martin, Laurent Moll | 2014-07-22 |
| 8645557 | System of interconnections for external functional blocks on a chip provided with a single configurable communication protocol | Cesar Douady | 2014-02-04 |
| 8441931 | Method and device for managing priority during the transmission of a message | Cesar Douady | 2013-05-14 |
| 8316171 | Network on chip (NoC) with QoS features | Philippe Martin, Jean-Jacques Lecler | 2012-11-20 |
| 8254380 | Managing messages transmitted in an interconnect network | Vincent Vacquerie | 2012-08-28 |
| 8031730 | System and method for transmitting a sequence of messages in an interconnection network | Cesar Douady | 2011-10-04 |
| 7769027 | Method and device for managing priority during the transmission of a message | Cesar Douady | 2010-08-03 |
| 7755920 | Electronic memory device | Pascal Godet, Luc Montperrus | 2010-07-13 |
| 7639704 | Message switching system | Luc Montperrus | 2009-12-29 |