Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11972189 | Interconnections for modular die designs | Siddharth Kamdar, Sanjay Jaisingh Arya, Manav Shah | 2024-04-30 |
| 11662765 | System for providing a low latency and fast switched cascaded dual phased lock loop (PLL) architecture for die-to-die / system-on-chip (SoC) interfaces | Mahalingam Nagarajan, Vaishnav Srinivas, Xavier Leloup, Michael Jäger | 2023-05-30 |
| 11520706 | Dram-aware caching | Alain Artieri, Rakesh Gupta, Subbarao Palacharla, Kedar Bhole, Laurent Moll +8 more | 2022-12-06 |
| 10606339 | Coherent interconnect power reduction using hardware controlled split snoop directories | Luc Montperrus, Philippe Boucard, Rakesh Gupta | 2020-03-31 |
| 10386904 | Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks | Jason Edward Podaima, Manokanthan Somasundaram, Sina Dena, Paul Christopher John Wiercienski, Bohuslav Rychlik +4 more | 2019-08-20 |
| 9910799 | Interconnect distributed virtual memory (DVM) message preemptive responding | Jason Edward Podaima, Manokanthan Somasundaram, Bohuslav Rychlik, Thomas Zeng, Jaya Prakash Subramaniam Ganasan +1 more | 2018-03-06 |