Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10386904 | Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks | Jason Edward Podaima, Christophe Avoinne, Manokanthan Somasundaram, Sina Dena, Paul Christopher John Wiercienski +4 more | 2019-08-20 |
| 9990291 | Avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols | Hien Minh Le, Thuong Quang Truong, Kun Xu, Cesar Aaron Ramirez | 2018-06-05 |
| 9921962 | Maintaining cache coherency using conditional intervention among multiple master devices | Kun Xu, Thuong Quang Truong, Hien Minh Le, Cesar Aaron Ramirez | 2018-03-20 |
| 9910799 | Interconnect distributed virtual memory (DVM) message preemptive responding | Christophe Avoinne, Jason Edward Podaima, Manokanthan Somasundaram, Bohuslav Rychlik, Thomas Zeng +1 more | 2018-03-06 |
| 9594713 | Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media | Randall Pascarella, Thuong Quang Truong, Gurushankar Rajamani, Joseph Gerald McDonald, Thomas Philip Speier | 2017-03-14 |