Issued Patents All Time
Showing 1–25 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9990291 | Avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols | Hien Minh Le, Kun Xu, Jaya Prakash Subramaniam Ganasan, Cesar Aaron Ramirez | 2018-06-05 |
| 9921962 | Maintaining cache coherency using conditional intervention among multiple master devices | Kun Xu, Jaya Prakash Subramaniam Ganasan, Hien Minh Le, Cesar Aaron Ramirez | 2018-03-20 |
| 9594713 | Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media | Randall Pascarella, Jaya Prakash Subramaniam Ganasan, Gurushankar Rajamani, Joseph Gerald McDonald, Thomas Philip Speier | 2017-03-14 |
| 8601193 | Performance monitor design for instruction profiling using shared counters | Etai Adar, Srinivasan Ramani, Eric F. Robinson | 2013-12-03 |
| 8589922 | Performance monitor design for counting events generated by thread groups | Etai Adar, Srinivasan Ramani, Eric F. Robinson | 2013-11-19 |
| 8489787 | Sharing sampled instruction address registers for efficient instruction sampling in massively multithreaded processors | Etai Adar, Russell D. Hoover, Srinivasan Ramani, Eric F. Robinson | 2013-07-16 |
| 8397029 | System and method for cache coherency in a multiprocessor system | Richard Nicholas, Jason A. Cox, Robert J. Dorsey, Hien Minh Le, Eric F. Robinson | 2013-03-12 |
| 8296520 | System and method for optimizing neighboring cache usage in a multiprocessor environment | Hien Minh Le, Jason A. Cox, Robert J. Dorsey, Richard Nicholas, Eric F. Robinson | 2012-10-23 |
| 8024489 | System for communicating command parameters between a processor and a memory flow controller | Michael Norman Day, Charles Johns, Peichun Peter Liu, Todd Swanson | 2011-09-20 |
| 8015565 | Preventing livelocks in processor selection of load requests | Richard W. Doing, John R. Patty, Steven R. Testa | 2011-09-06 |
| 7877550 | Bus controller initiated write-through mechanism with hardware automatically generated clean command | Jonathan James DeMent, Kerey Michelle Tassin | 2011-01-25 |
| 7869459 | Communicating instructions and data between a processor and external devices | Michael Norman Day, Charles Johns, John Liberty, Todd Swanson | 2011-01-11 |
| 7836257 | System and method for cache line replacement selection in a multiprocessor environment | Robert J. Dorsey, Jason A. Cox, Hien Minh Le, Richard Nicholas, Eric F. Robinson | 2010-11-16 |
| 7818509 | Combined response cancellation for load command | Brian Mitchell Bass, Eric F. Robinson | 2010-10-19 |
| 7814281 | Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment | Michael Norman Day, Charles Ray Johns, James Allan Kahle, Peichum Peter Liu | 2010-10-12 |
| 7778271 | Method for communicating instructions and data between a processor and external devices | Michael Norman Day, Charles Johns, John Liberty, Todd Swanson | 2010-08-17 |
| 7725660 | Directory for multi-node coherent bus | Gary Dale Carpenter, Scott Douglas Clark, Bernard C. Drerup, Russell D. Hoover, Charles Ray Johns +2 more | 2010-05-25 |
| 7725618 | Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment | Michael Norman Day, Charles Ray Johns, Peichun Peter Liu, Takeshi Yamazaki | 2010-05-25 |
| 7721123 | Method and apparatus for managing the power consumption of a data processing system | Shigehiro Asano, Jeffrey Douglas Brown, Michael Norman Day, Charles Ray Johns, James Allan Kahle +2 more | 2010-05-18 |
| 7689870 | Efficient and flexible trace trigger handling for non-concurrent events | Jason A. Cox, Keith A. DeWeese, Robert J. Dorsey, Eric F. Robinson, Mark J. Wolski | 2010-03-30 |
| 7669013 | Directory for multi-node coherent bus | Gary Dale Carpenter, Scott Douglas Clark, Bernard C. Drerup, Russell D. Hoover, Charles Ray Johns +2 more | 2010-02-23 |
| 7657667 | Method to provide cache management commands for a DMA controller | Charles Ray Johns, James Allan Kahle, Peichun Peter Liu | 2010-02-02 |
| 7613841 | Systems and methods for reducing data storage in devices using multi-phase data transactions | Shigehiro Asano | 2009-11-03 |
| 7596665 | Mechanism for a processor to use locking cache as part of system memory | Michael Norman Day, Charles Johns | 2009-09-29 |
| 7590802 | Direct deposit using locking cache | Michael Norman Day, Charles Johns | 2009-09-15 |