| 8244979 |
System and method for cache-locking mechanism using translation table attributes for replacement class ID determination |
Adam P. Burns, Jason N. Dale, Gavin B. Meil |
2012-08-14 |
$4,482,000 |
| 8230495 |
Method for security in electronically fused encryption keys |
Robert W. Berry, Jr., John Liberty |
2012-07-24 |
$4,383,000 |
| 8099579 |
System and method for cache-locking mechanism using segment table attributes for replacement class ID determination |
Adam P. Burns, Jason N. Dale, Gavin B. Meil |
2012-01-17 |
$12,258,000 |
| 8046574 |
Secure boot across a plurality of processors |
Jason N. Dale, Clark M. O'Niell, Christopher J. Spandikow |
2011-10-25 |
$17,275,000 |
| 8046573 |
Masking a hardware boot sequence |
Jason N. Dale, Clark M. O'Niell, Steven L. Roberts |
2011-10-25 |
$17,275,000 |
| 8037293 |
Selecting a random processor to boot on a multiprocessor system |
Jason N. Dale, Clark M. O'Niell, Christopher J. Spandikow |
2011-10-11 |
$5,277,000 |
| 8028151 |
Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines |
Christopher M. Abernathy, Ronald P. Hall, Albert J. Van Norstrand, Jr. |
2011-09-27 |
$6,526,000 |
| 7917347 |
Generating a worst case current waveform for testing of integrated circuit devices |
Makoto Aikawa, Sang Hoo Dhong, Brian Flachs, Gilles Gervais, Iwao Takiguchi +1 more |
2011-03-29 |
$5,031,000 |
| 7913070 |
Time-of-life counter for handling instruction flushes from a queue |
Christopher M. Abernathy, Ronald P. Hall, Robert Alan Philhower, David Shippy |
2011-03-22 |
$5,211,000 |
| 7877550 |
Bus controller initiated write-through mechanism with hardware automatically generated clean command |
Kerey Michelle Tassin, Thuong Quang Truong |
2011-01-25 |
$4,442,000 |
| 7831808 |
Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor |
Christopher M. Abernathy, Ronald P. Hall, David Shippy |
2010-11-09 |
$6,046,000 |
| 7779273 |
Booting a multiprocessor device based on selection of encryption keys to be provided to processors |
Jason N. Dale, Clark M. O'Niell, Christopher J. Spandikow |
2010-08-17 |
$4,695,000 |
| 7774616 |
Masking a boot sequence by providing a dummy processor |
Jason N. Dale, Clark M. O'Niell, Steven L. Roberts |
2010-08-10 |
$5,029,000 |
| 7774617 |
Masking a boot sequence by providing a dummy processor |
Jason N. Dale, Clark M. O'Niell, Steven L. Roberts |
2010-08-10 |
$5,029,000 |
| 7739573 |
Voltage identifier sorting |
Sang Hoo Dhong, Gilles Gervais, Alain Loiseau, Kirk D. Peterson, John L. Sinchak |
2010-06-15 |
$4,416,000 |
| 7711903 |
Preloading translation buffers |
Michael Norman Day, Charles Johns |
2010-05-04 |
$4,679,000 |
| 7681056 |
Dynamic power management in a processor design |
Christopher M. Abernathy, Ronald P. Hall, Robert Alan Philhower, David Shippy |
2010-03-16 |
$7,988,000 |
| 7594104 |
System and method for masking a hardware boot sequence |
Jason N. Dale, Clark M. O'Niell, Steven L. Roberts |
2009-09-22 |
$18,778,000 |
| 7519780 |
System and method for reducing store latency in symmetrical multiprocessor systems |
Roy Moonseuk Kim, Alvan W. Ng, Kevin C. Stelzer, Thuong Quang Truong |
2009-04-14 |
$4,368,000 |
| 7516275 |
Pseudo-LRU virtual counter for a locking cache |
Ronald P. Hall, Brian Patrick Hanley, Kevin C. Stelzer |
2009-04-07 |
$6,511,000 |
| 7490224 |
Time-of-life counter design for handling instruction flushes from a queue |
Christopher M. Abernathy, Ronald P. Hall, Robert Alan Philhower, David Shippy |
2009-02-10 |
$5,620,000 |
| 7475232 |
Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines |
Christopher M. Abernathy, Ronald P. Hall, Albert J. Van Norstrand, Jr. |
2009-01-06 |
$2,860,000 |
| 7472229 |
Bus controller initiated write-through mechanism |
Kerey Michelle Tassin, Thuong Quang Truong |
2008-12-30 |
$5,097,000 |
| 7447602 |
System and method for sorting processors based on thermal design point |
Douglas H. Bradley, Sang Hoo Dhong, Brian Flachs, Gilles Gervais, Yoichi Nishino |
2008-11-04 |
$6,466,000 |
| 7401242 |
Dynamic power management in a processor design |
Christopher M. Abernathy, Ronald P. Hall, Robert Alan Philhower, David Shippy |
2008-07-15 |
$7,406,000 |
