Issued Patents All Time
Showing 1–25 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11768684 | Compaction of architected registers in a simultaneous multithreading processor | Steven J. Battle, Dung Q. Nguyen, Tu-An T. Nguyen, Cliff Kucharski | 2023-09-26 |
| 11144319 | Redistribution of architected states for a processor register file | Steven J. Battle, Susan E. Eisen, Dung Q. Nguyen, Salma Ayub, Kent Li +2 more | 2021-10-12 |
| 11068274 | Prioritized instructions in an instruction completion table of a simultaneous multithreading processor | Kenneth L. Ward, Susan E. Eisen, Dung Q. Nguyen, Glenn O. Kincaid, Christopher M. Mueller | 2021-07-20 |
| 10983800 | Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti +1 more | 2021-04-20 |
| 10909034 | Issue queue snooping for asynchronous flush and restore of distributed history buffer | David R. Terry, Dung Q. Nguyen, Brian W. Thompto, Joshua W. Bowman, Steven J. Battle +2 more | 2021-02-02 |
| 10884742 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2021-01-05 |
| 10831492 | Most favored branch issue | Salma Ayub, Glenn O. Kincaid, Christopher M. Mueller, Dung Q. Nguyen, Eula Faye Abalos Tolentino +1 more | 2020-11-10 |
| 10831481 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2020-11-10 |
| 10552162 | Variable latency flush filtering | Glenn O. Kincaid, David S. Levitan | 2020-02-04 |
| 10545765 | Multi-level history buffer for transaction memory in a microprocessor | Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q. Nguyen +1 more | 2020-01-28 |
| 10528352 | Blocking instruction fetching in a computer processor | Bryan G. Hickerson, Sheldon B. Levenstein, David S. Levitan | 2020-01-07 |
| 10496406 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2019-12-03 |
| 10467008 | Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor | David S. Levitan, Mehul Patel, Phillip G. Williams | 2019-11-05 |
| 10409598 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2019-09-10 |
| 10387154 | Thread migration using a microcode engine of a multi-slice processor | James Wilson Bishop, Marcy E. Byers, Steven R. Carlough, Paul M. Kennedy, Phillip G. Williams | 2019-08-20 |
| 10387686 | Hardware based isolation for secure execution of virtual machines | Richard H. Boivie, Bradly G. Frey, William E. Hall, Benjamin Herrenschmidt, Guerney D. H. Hunt +3 more | 2019-08-20 |
| 10379867 | Asynchronous flush and restore of distributed history buffer | David R. Terry, Dung Q. Nguyen, Brian W. Thompto, Joshua W. Bowman, Steven J. Battle +2 more | 2019-08-13 |
| 10353710 | Techniques for predicting a target address of an indirect branch instruction | Richard J. Eickemeyer, Naga P. Gorti, David S. Levitan | 2019-07-16 |
| 10248555 | Managing an effective address table in a multi-slice processor | Akash V. Giri, David S. Levitan, Mehul Patel | 2019-04-02 |
| 10241905 | Managing an effective address table in a multi-slice processor | Akash V. Giri, David S. Levitan, Mehul Patel | 2019-03-26 |
| 10169046 | Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction | Maarten J. Boersma, Robert A. Cordes, David A. Hrusecky, Jennifer L. Molnar, Brian W. Thompto +1 more | 2019-01-01 |
| 10157064 | Processing of multiple instruction streams in a parallel slice processor | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti +1 more | 2018-12-18 |
| 10083039 | Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti +1 more | 2018-09-25 |
| 10073697 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2018-09-11 |
| 10067763 | Handling unaligned load operations in a multi-slice computer processor | Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra +2 more | 2018-09-04 |