Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11366671 | Completion mechanism for a microprocessor instruction completion table | Susan E. Eisen, Dung Q. Nguyen, Glenn O. Kincaid, Joe Lee, Deepak Singh | 2022-06-21 |
| 11327757 | Processor providing intelligent management of values buffered in overlaid architected and non-architected register files | Steven J. Battle, Kurt A. Feiste, Susan E. Eisen, Dung Q. Nguyen, Christian Zoellin +4 more | 2022-05-10 |
| 11269647 | Finish status reporting for a simultaneous multithreading processor using an instruction completion table | Susan E. Eisen, Dung Q. Nguyen, Glenn O. Kincaid, Christopher M. Mueller, Tu-An T. Nguyen +2 more | 2022-03-08 |
| 11119772 | Check pointing of accumulator register results in a microprocessor | Steven J. Battle, Brian D. Barrick, Susan E. Eisen, Andreas Wagner, Dung Q. Nguyen +2 more | 2021-09-14 |
| 11086630 | Finish exception handling of an instruction completion table | Susan E. Eisen, Christopher M. Mueller, Glenn O. Kincaid, Dhivya Jeganathan | 2021-08-10 |
| 11068274 | Prioritized instructions in an instruction completion table of a simultaneous multithreading processor | Susan E. Eisen, Dung Q. Nguyen, Albert J. Van Norstrand, Jr., Glenn O. Kincaid, Christopher M. Mueller | 2021-07-20 |
| 11030018 | On-demand multi-tiered hang buster for SMT microprocessor | Steven J. Battle, Dung Q. Nguyen, Susan E. Eisen, Eula Faye Abalos Tolentino, Cliff Kucharski +2 more | 2021-06-08 |
| 10977034 | Instruction completion table with ready-to-complete vector | Susan E. Eisen, Glenn O. Kincaid, Dung Q. Nguyen, Deepak Singh, Gaurav Mittal +1 more | 2021-04-13 |
| 10929144 | Speculatively releasing store data before store instruction completion in a processor | Hung Q. Le, Dung Q. Nguyen, Bryan Lloyd | 2021-02-23 |
| 10901743 | Speculative execution of both paths of a weakly predicted branch instruction | Dung Q. Nguyen, Susan E. Eisen, Hung Q. Le | 2021-01-26 |
| 10877763 | Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor | Bryan Lloyd, Brian D. Barrick, Kurt A. Feiste, Hung Q. Le, Dung Q. Nguyen | 2020-12-29 |
| 10831489 | Mechanism for completing atomic instructions in a microprocessor | Susan E. Eisen, Dung Q. Nguyen, Glenn O. Kincaid, Joe Lee, Deepak Singh | 2020-11-10 |
| 10831492 | Most favored branch issue | Salma Ayub, Glenn O. Kincaid, Christopher M. Mueller, Dung Q. Nguyen, Eula Faye Abalos Tolentino +1 more | 2020-11-10 |
| 10761856 | Instruction completion table containing entries that share instruction tags | Dung Q. Nguyen, Hung Q. Le, Susan E. Eisen | 2020-09-01 |
| 10725786 | Completion mechanism for a microprocessor instruction completion table | Susan E. Eisen, Dung Q. Nguyen, Glenn O. Kincaid, Joe Lee, Deepak Singh | 2020-07-28 |
| 10713057 | Mechanism to stop completions using stop codes in an instruction completion table | Dung Q. Nguyen, Susan E. Eisen, Christopher M. Mueller, Joe Lee, Deepak Singh | 2020-07-14 |
| 10552165 | Efficiently managing speculative finish tracking and error handling for load instructions | Susan E. Eisen, David A. Hrusecky, Christopher M. Mueller, Dung Q. Nguyen, A. James Van Norstrand, Jr. | 2020-02-04 |
| 10423423 | Efficiently managing speculative finish tracking and error handling for load instructions | Susan E. Eisen, David A. Hrusecky, Christopher M. Mueller, Dung Q. Nguyen, A. James Van Norstrand, Jr. | 2019-09-24 |
| 10169046 | Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction | Maarten J. Boersma, Robert A. Cordes, David A. Hrusecky, Jennifer L. Molnar, Brian W. Thompto +1 more | 2019-01-01 |
| 10108423 | History buffer with single snoop tag for multiple-field registers | Michael J. Genden, Dung Q. Nguyen | 2018-10-23 |
| 9996353 | Universal history buffer to support multiple register types | Michael J. Genden, Hung Q. Le, Dung Q. Nguyen | 2018-06-12 |
| 9971604 | History buffer for multiple-field registers | Sundeep Chadha, Michael J. Genden, Dung Q. Nguyen, David R. Terry | 2018-05-15 |
| 9971687 | Operation of a multi-slice processor with history buffers storing transaction memory state information | Brian D. Barrick, Susan E. Eisen, Kurt A. Feiste, Dung Q. Nguyen, Jing Zhang | 2018-05-15 |
| 9798549 | Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction | Maarten J. Boersma, Robert A. Cordes, David A. Hrusecky, Jennifer L. Molnar, Brian W. Thompto +1 more | 2017-10-24 |
| 7870406 | Method and apparatus for frequency independent processor utilization recording register in a simultaneously multi-threaded processor | Richard Louis Arndt, Balaram Sinharoy, Scott Barnett Swaney | 2011-01-11 |