Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11775337 | Prioritization of threads in a simultaneous multithreading processor core | Bryan Lloyd, Guy L. Guthrie, Susan E. Eisen, Luke Murray | 2023-10-03 |
| 11327757 | Processor providing intelligent management of values buffered in overlaid architected and non-architected register files | Steven J. Battle, Kurt A. Feiste, Susan E. Eisen, Dung Q. Nguyen, Christian Zoellin +4 more | 2022-05-10 |
| 11086630 | Finish exception handling of an instruction completion table | Kenneth L. Ward, Susan E. Eisen, Christopher M. Mueller, Glenn O. Kincaid | 2021-08-10 |
| 10719056 | Merging status and control data in a reservation station | Brian D. Barrick, Joshua W. Bowman, Jeffrey C. Brownscheidle, Sundeep Chadha, Michael J. Genden +2 more | 2020-07-21 |
| 10649779 | Variable latency pipe for interleaving instruction tags in a microprocessor | Salma Ayub, Josh Bowman, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen | 2020-05-12 |
| 10613868 | Variable latency pipe for interleaving instruction tags in a microprocessor | Salma Ayub, Josh Bowman, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen | 2020-04-07 |
| 10489253 | On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor | Steven J. Battle, Joshua W. Bowman, Sundeep Chadha, Cliff Kucharski, Dung Q. Nguyen +2 more | 2019-11-26 |
| 10445100 | Broadcasting messages between execution slices for issued instructions indicating when execution results are ready | Salma Ayub, Joshua W. Bowman, Jeffrey C. Brownscheidle, Sundeep Chadha, Dung Q. Nguyen +2 more | 2019-10-15 |
| 10176038 | Partial ECC mechanism for a byte-write capable register | Dung Q. Nguyen, Jose Angel Paredes, David R. Terry, Brian W. Thompto | 2019-01-08 |
| 10031757 | Operation of a multi-slice processor implementing a mechanism to overcome a system hang | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen, Salim A. Shah | 2018-07-24 |
| 9985656 | Generating ECC values for byte-write capable registers | Dung Q. Nguyen, Jose Angel Paredes, David R. Terry, Brian W. Thompto | 2018-05-29 |
| 9983879 | Operation of a multi-slice processor implementing dynamic switching of instruction issuance order | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen, Salim A. Shah | 2018-05-29 |
| 9985655 | Generating ECC values for byte-write capable registers | Dung Q. Nguyen, Jose Angel Paredes, David R. Terry, Brian W. Thompto | 2018-05-29 |
| 9959123 | Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor | Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dung Q. Nguyen, David R. Terry +1 more | 2018-05-01 |
| 9928073 | Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor | Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dung Q. Nguyen, David R. Terry +1 more | 2018-03-27 |
| 9921833 | Determining of validity of speculative load data after a predetermined period of time in a multi-slice processor | Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dung Q. Nguyen, David R. Terry +1 more | 2018-03-20 |
| 9858078 | Speculative load data in byte-write capable register file and history buffer for a multi-slice microprocessor | Joshua W. Bowman, Sundeep Chadha, Michael J. Genden, Dung Q. Nguyen, David R. Terry +1 more | 2018-01-02 |
| 9766975 | Partial ECC handling for a byte-write capable register | Dung Q. Nguyen, Jose Angel Paredes, David R. Terry, Brian W. Thompto | 2017-09-19 |
| 9639418 | Parity protection of a register | Joshua W. Bowman, Sam Gat-Shang Chu, Cliff Kucharski, Dung Q. Nguyen, David R. Terry | 2017-05-02 |