Issued Patents All Time
Showing 25 most recent of 81 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12061909 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Dung Q. Nguyen +1 more | 2024-08-13 |
| 11748104 | Microprocessor that fuses load and compare instructions | Bryan Lloyd, David A. Hrusecky, Dung Q. Nguyen, Christian Zoellin, Brian W. Thompto +2 more | 2023-09-05 |
| 11734010 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Dung Q. Nguyen +1 more | 2023-08-22 |
| 11163571 | Fusion to enhance early address generation of load instructions in a microprocessor | Brian D. Barrick, Sheldon B. Levenstein, Phillip G. Williams, Niels Fricke, Dung Q. Nguyen +2 more | 2021-11-02 |
| 11150909 | Energy efficient source operand issue | Jeffrey C. Brownscheidle, Maureen A. Delaney, Dung Q. Nguyen | 2021-10-19 |
| 11150907 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Dung Q. Nguyen +1 more | 2021-10-19 |
| 11138050 | Operation of a multi-slice processor implementing a hardware level transfer of an execution thread | Brian D. Barrick, James Wilson Bishop, Marcy E. Byers, Cliff Kucharski, Dung Q. Nguyen +2 more | 2021-10-05 |
| 10983797 | Program instruction scheduling | Christian Zoellin, Phillip G. Williams, Brian W. Thompto, Dung Q. Nguyen, Hung Q. Le +3 more | 2021-04-20 |
| 10942745 | Fast multi-width instruction issue in parallel slice processor | Salma Ayub, Jeffrey C. Brownscheidle, Dung Q. Nguyen, Tu-An T. Nguyen, Salim A. Shah +1 more | 2021-03-09 |
| 10909034 | Issue queue snooping for asynchronous flush and restore of distributed history buffer | David R. Terry, Dung Q. Nguyen, Brian W. Thompto, Joshua W. Bowman, Steven J. Battle +2 more | 2021-02-02 |
| 10884742 | Handling unaligned load operations in a multi-slice computer processor | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2021-01-05 |
| 10831481 | Handling unaligned load operations in a multi-slice computer processor | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2020-11-10 |
| 10719056 | Merging status and control data in a reservation station | Brian D. Barrick, Joshua W. Bowman, Jeffrey C. Brownscheidle, Michael J. Genden, Dhivya Jeganathan +2 more | 2020-07-21 |
| 10671399 | Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core | Maarten J. Boersma, Kurt A. Feiste, Michael J. Genden, Michael K. Kroener, David R. Terry | 2020-06-02 |
| 10671398 | Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core | Maarten J. Boersma, Kurt A. Feiste, Michael J. Genden, Michael K. Kroener, David R. Terry | 2020-06-02 |
| 10649779 | Variable latency pipe for interleaving instruction tags in a microprocessor | Salma Ayub, Josh Bowman, Dhivya Jeganathan, Cliff Kucharski, Dung Q. Nguyen | 2020-05-12 |
| 10613868 | Variable latency pipe for interleaving instruction tags in a microprocessor | Salma Ayub, Josh Bowman, Dhivya Jeganathan, Cliff Kucharski, Dung Q. Nguyen | 2020-04-07 |
| 10496406 | Handling unaligned load operations in a multi-slice computer processor | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2019-12-03 |
| 10489253 | On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor | Steven J. Battle, Joshua W. Bowman, Dhivya Jeganathan, Cliff Kucharski, Dung Q. Nguyen +2 more | 2019-11-26 |
| 10445100 | Broadcasting messages between execution slices for issued instructions indicating when execution results are ready | Salma Ayub, Joshua W. Bowman, Jeffrey C. Brownscheidle, Dhivya Jeganathan, Dung Q. Nguyen +2 more | 2019-10-15 |
| 10409598 | Handling unaligned load operations in a multi-slice computer processor | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2019-09-10 |
| 10379867 | Asynchronous flush and restore of distributed history buffer | David R. Terry, Dung Q. Nguyen, Brian W. Thompto, Joshua W. Bowman, Steven J. Battle +2 more | 2019-08-13 |
| 10318356 | Operation of a multi-slice processor implementing a hardware level transfer of an execution thread | Brian D. Barrick, James Wilson Bishop, Marcy E. Byers, Cliff Kucharski, Dung Q. Nguyen +2 more | 2019-06-11 |
| 10318419 | Flush avoidance in a load store unit | David A. Hrusecky, Elizabeth A. McGlone, George W. Rohrbaugh, III, Shih-Hsiung S. Tung | 2019-06-11 |
| 10282207 | Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction | Brian D. Barrick, Michael J. Genden, Jerry Y. Lu, Dung Q. Nguyen, Nasrin Sultana +2 more | 2019-05-07 |