| 11941398 |
Fast mapper restore for flush in processor |
Brian D. Barrick, Steven J. Battle, Dung Q. Nguyen, Susan E. Eisen, Salma Ayub |
2024-03-26 |
| 11768684 |
Compaction of architected registers in a simultaneous multithreading processor |
Steven J. Battle, Dung Q. Nguyen, Albert J. Van Norstrand, Jr., Tu-An T. Nguyen |
2023-09-26 |
| 11561794 |
Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry |
Steven J. Battle, Brian W. Thompto, Dung Q. Nguyen, Susan E. Eisen, Salma Ayub |
2023-01-24 |
| 11194578 |
Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor |
Steven J. Battle, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard +2 more |
2021-12-07 |
| 11188332 |
System and handling of register data in processors |
Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen +2 more |
2021-11-30 |
| 11144364 |
Supporting speculative microprocessor instruction execution |
Steven J. Battle, Brandon Goddard, Dung Q. Nguyen, Joshua W. Bowman, Brian D. Barrick +2 more |
2021-10-12 |
| 11138050 |
Operation of a multi-slice processor implementing a hardware level transfer of an execution thread |
Brian D. Barrick, James Wilson Bishop, Marcy E. Byers, Sundeep Chadha, Dung Q. Nguyen +2 more |
2021-10-05 |
| 11093282 |
Register file write using pointers |
Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q. Nguyen +1 more |
2021-08-17 |
| 11030018 |
On-demand multi-tiered hang buster for SMT microprocessor |
Steven J. Battle, Dung Q. Nguyen, Susan E. Eisen, Kenneth L. Ward, Eula Faye Abalos Tolentino +2 more |
2021-06-08 |
| 10949205 |
Implementation of execution compression of instructions in slice target register file mapper |
Joshua W. Bowman, Dung Q. Nguyen, Hung Q. Le, Brian W. Thompto, Maureen A. Delaney +1 more |
2021-03-16 |
| 10649779 |
Variable latency pipe for interleaving instruction tags in a microprocessor |
Salma Ayub, Josh Bowman, Sundeep Chadha, Dhivya Jeganathan, Dung Q. Nguyen |
2020-05-12 |
| 10613868 |
Variable latency pipe for interleaving instruction tags in a microprocessor |
Salma Ayub, Josh Bowman, Sundeep Chadha, Dhivya Jeganathan, Dung Q. Nguyen |
2020-04-07 |
| 10489253 |
On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor |
Steven J. Battle, Joshua W. Bowman, Sundeep Chadha, Dhivya Jeganathan, Dung Q. Nguyen +2 more |
2019-11-26 |
| 10318356 |
Operation of a multi-slice processor implementing a hardware level transfer of an execution thread |
Brian D. Barrick, James Wilson Bishop, Marcy E. Byers, Sundeep Chadha, Dung Q. Nguyen +2 more |
2019-06-11 |
| 10289415 |
Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data |
Susan E. Eisen, Hung Q. Le, Dung Q. Nguyen, David R. Terry |
2019-05-14 |
| 10282205 |
Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions |
Susan E. Eisen, Hung Q. Le, Dung Q. Nguyen, David R. Terry |
2019-05-07 |
| 10255071 |
Method and apparatus for managing a speculative transaction in a processing unit |
Salma Ayub, Susan E. Eisen, Glenn O. Kincaid, Christopher M. Mueller, Dung Q. Nguyen +1 more |
2019-04-09 |
| 10248421 |
Operation of a multi-slice processor with reduced flush and restore latency |
Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Sundeep Chadha, Dung Q. Nguyen +2 more |
2019-04-02 |
| 10241790 |
Operation of a multi-slice processor with reduced flush and restore latency |
Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Sundeep Chadha, Dung Q. Nguyen +2 more |
2019-03-26 |
| 10073699 |
Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture |
Susan E. Eisen, Hung Q. Le, Dung Q. Nguyen, David R. Terry |
2018-09-11 |
| 9747217 |
Distributed history buffer flush and restore handling in a parallel slice design |
Salma Ayub, Sundeep Chadha, Michael J. Genden, Dung Q. Nguyen, David R. Terry |
2017-08-29 |
| 9740620 |
Distributed history buffer flush and restore handling in a parallel slice design |
Salma Ayub, Sundeep Chadha, Michael J. Genden, Dung Q. Nguyen, David R. Terry |
2017-08-22 |
| 9639418 |
Parity protection of a register |
Joshua W. Bowman, Sam Gat-Shang Chu, Dhivya Jeganathan, Dung Q. Nguyen, David R. Terry |
2017-05-02 |
