Issued Patents All Time
Showing 25 most recent of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12204902 | Routing instruction results to a register block of a subdivided register file based on register block utilization rate | Kurt A. Feiste, Brian W. Thompto, Salma Ayub, Dung Q. Nguyen | 2025-01-21 |
| 11941398 | Fast mapper restore for flush in processor | Brian D. Barrick, Steven J. Battle, Dung Q. Nguyen, Cliff Kucharski, Salma Ayub | 2024-03-26 |
| 11775337 | Prioritization of threads in a simultaneous multithreading processor core | Bryan Lloyd, Guy L. Guthrie, Dhivya Jeganathan, Luke Murray | 2023-10-03 |
| 11561794 | Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry | Steven J. Battle, Brian W. Thompto, Dung Q. Nguyen, Cliff Kucharski, Salma Ayub | 2023-01-24 |
| 11403109 | Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor | Steven J. Battle, Khandker N. Adeeb, Brian D. Barrick, Joshua W. Bowman, Brandon Goddard +2 more | 2022-08-02 |
| 11366671 | Completion mechanism for a microprocessor instruction completion table | Kenneth L. Ward, Dung Q. Nguyen, Glenn O. Kincaid, Joe Lee, Deepak Singh | 2022-06-21 |
| 11360779 | Logical register recovery within a processor | Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Brandon Goddard +2 more | 2022-06-14 |
| 11327766 | Instruction dispatch routing | Eric M. Schwarz, Brian W. Thompto, Kurt A. Feiste, Michael J. Genden, Dung Q. Nguyen | 2022-05-10 |
| 11327757 | Processor providing intelligent management of values buffered in overlaid architected and non-architected register files | Steven J. Battle, Kurt A. Feiste, Dung Q. Nguyen, Christian Zoellin, Kent Li +4 more | 2022-05-10 |
| 11269647 | Finish status reporting for a simultaneous multithreading processor using an instruction completion table | Kenneth L. Ward, Dung Q. Nguyen, Glenn O. Kincaid, Christopher M. Mueller, Tu-An T. Nguyen +2 more | 2022-03-08 |
| 11256507 | Thread transition management | Christopher M. Abernathy, Mary D. Brown, James Allan Kahle, Hung Q. Le, Dung Q. Nguyen | 2022-02-22 |
| 11194578 | Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor | Steven J. Battle, Brian D. Barrick, Joshua W. Bowman, Brandon Goddard, Cliff Kucharski +2 more | 2021-12-07 |
| 11188332 | System and handling of register data in processors | Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Brandon Goddard +2 more | 2021-11-30 |
| 11144364 | Supporting speculative microprocessor instruction execution | Steven J. Battle, Brandon Goddard, Dung Q. Nguyen, Joshua W. Bowman, Brian D. Barrick +2 more | 2021-10-12 |
| 11144319 | Redistribution of architected states for a processor register file | Steven J. Battle, Dung Q. Nguyen, Salma Ayub, Albert J. Van Norstrand, Jr., Kent Li +2 more | 2021-10-12 |
| 11119772 | Check pointing of accumulator register results in a microprocessor | Steven J. Battle, Brian D. Barrick, Andreas Wagner, Dung Q. Nguyen, Brian W. Thompto +2 more | 2021-09-14 |
| 11086630 | Finish exception handling of an instruction completion table | Kenneth L. Ward, Christopher M. Mueller, Glenn O. Kincaid, Dhivya Jeganathan | 2021-08-10 |
| 11068274 | Prioritized instructions in an instruction completion table of a simultaneous multithreading processor | Kenneth L. Ward, Dung Q. Nguyen, Albert J. Van Norstrand, Jr., Glenn O. Kincaid, Christopher M. Mueller | 2021-07-20 |
| 11068267 | High bandwidth logical register flush recovery | Steven J. Battle, Brandon Goddard, Dung Q. Nguyen, Joshua W. Bowman, Brian D. Barrick +2 more | 2021-07-20 |
| 11030018 | On-demand multi-tiered hang buster for SMT microprocessor | Steven J. Battle, Dung Q. Nguyen, Kenneth L. Ward, Eula Faye Abalos Tolentino, Cliff Kucharski +2 more | 2021-06-08 |
| 10996995 | Saving and restoring a transaction memory state | Steven J. Battle, Dung Q. Nguyen, Hung Q. Le, James Wilson Bishop, Brian W. Thompto | 2021-05-04 |
| 10977034 | Instruction completion table with ready-to-complete vector | Kenneth L. Ward, Glenn O. Kincaid, Dung Q. Nguyen, Deepak Singh, Gaurav Mittal +1 more | 2021-04-13 |
| 10956158 | System and handling of register data in processors | Steven J. Battle, Khandker N. Adeeb, Brian D. Barrick, Joshua W. Bowman, Thao T. Doan +2 more | 2021-03-23 |
| 10949213 | Logical register recovery within a processor | Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Brandon Goddard +2 more | 2021-03-16 |
| 10901743 | Speculative execution of both paths of a weakly predicted branch instruction | Kenneth L. Ward, Dung Q. Nguyen, Hung Q. Le | 2021-01-26 |