Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12204902 | Routing instruction results to a register block of a subdivided register file based on register block utilization rate | Brian W. Thompto, Susan E. Eisen, Salma Ayub, Dung Q. Nguyen | 2025-01-21 |
| 11327766 | Instruction dispatch routing | Eric M. Schwarz, Brian W. Thompto, Michael J. Genden, Dung Q. Nguyen, Susan E. Eisen | 2022-05-10 |
| 11327757 | Processor providing intelligent management of values buffered in overlaid architected and non-architected register files | Steven J. Battle, Susan E. Eisen, Dung Q. Nguyen, Christian Zoellin, Kent Li +4 more | 2022-05-10 |
| 11144319 | Redistribution of architected states for a processor register file | Steven J. Battle, Susan E. Eisen, Dung Q. Nguyen, Salma Ayub, Albert J. Van Norstrand, Jr. +2 more | 2021-10-12 |
| 10970079 | Parallel dispatching of multi-operation instructions in a multi-slice computer processor | Michael J. Genden, Paul M. Kennedy, Dung Q. Nguyen | 2021-04-06 |
| 10936321 | Instruction chaining | Joshua W. Bowman, Christopher M. Mueller, Dung Q. Nguyen, Deepak Singh, Brian W. Thompto | 2021-03-02 |
| 10877763 | Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor | Bryan Lloyd, Brian D. Barrick, Hung Q. Le, Dung Q. Nguyen, Kenneth L. Ward | 2020-12-29 |
| 10838728 | Parallel slice processor shadowing states of hardware threads across execution slices | Christopher M. Mueller, Dung Q. Nguyen, Eula A. Tolentino, Tien T. Tran, Jing Zhang | 2020-11-17 |
| 10740107 | Operation of a multi-slice processor implementing load-hit-store handling | Salma Ayub, Joshua W. Bowman, Jeffrey C. Brownscheidle, Dung Q. Nguyen, Salim A. Shah +1 more | 2020-08-11 |
| 10671399 | Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core | Maarten J. Boersma, Sundeep Chadha, Michael J. Genden, Michael K. Kroener, David R. Terry | 2020-06-02 |
| 10671398 | Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core | Maarten J. Boersma, Sundeep Chadha, Michael J. Genden, Michael K. Kroener, David R. Terry | 2020-06-02 |
| 10496412 | Parallel dispatching of multi-operation instructions in a multi-slice computer processor | Michael J. Genden, Paul M. Kennedy, Dung Q. Nguyen | 2019-12-03 |
| 10437756 | Operation of a multi-slice processor implementing datapath steering | Steven R. Carlough, Brian W. Thompto, Phillip G. Williams | 2019-10-08 |
| 10417152 | Operation of a multi-slice processor implementing datapath steering | Steven R. Carlough, Brian W. Thompto, Phillip G. Williams | 2019-09-17 |
| 10120683 | Supporting even instruction tag (‘ITAG’) requirements in a multi-slice processor using null internal operations (IOPs) | Steven R. Carlough, Paul M. Kennedy, Phillip G. Williams | 2018-11-06 |
| 10102001 | Parallel slice processor shadowing states of hardware threads across execution slices | Christopher M. Mueller, Dung Q. Nguyen, Eula A. Tolentino, Tien T. Tran, Jing Zhang | 2018-10-16 |
| 9977677 | Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port | Christopher M. Mueller, Dung Q. Nguyen, Eula Faye Abalos Tolentino, Tien T. Tran, Jing Zhang | 2018-05-22 |
| 9971687 | Operation of a multi-slice processor with history buffers storing transaction memory state information | Brian D. Barrick, Susan E. Eisen, Dung Q. Nguyen, Kenneth L. Ward, Jing Zhang | 2018-05-15 |
| 8200946 | Issue unit for placing a processor into a gradual slow mode of operation | Christopher M. Abernathy, Ronald P. Hall, Albert J. Van Norstrand, Jr. | 2012-06-12 |
| 8082423 | Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates | Christopher M. Abernathy, David Scott Ray, David Shippy, Albert J. Van Norstrand, Jr. | 2011-12-20 |
| 8041928 | Information handling system with real and virtual load/store instruction issue queue | William E. Burky, Dung Q. Nguyen, Balaram Sinharoy, Albert Thomas Williams | 2011-10-18 |
| 7953960 | Method and apparatus for delaying a load miss flush until issuing the dependent instruction | David Scott Ray, David Shippy, Albert J. Van Norstrand, Jr. | 2011-05-31 |
| 7949857 | Method and system for determining multiple unused registers in a processor | — | 2011-05-24 |
| 7818544 | Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition | Christopher M. Abernathy, Ronald P. Hall, Albert J. Van Norstrand, Jr. | 2010-10-19 |
| 7437539 | Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline | Christopher M. Abernathy, Ronald P. Hall, Albert J. Van Norstrand, Jr. | 2008-10-14 |