Issued Patents All Time
Showing 26–50 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10831489 | Mechanism for completing atomic instructions in a microprocessor | Kenneth L. Ward, Dung Q. Nguyen, Glenn O. Kincaid, Joe Lee, Deepak Singh | 2020-11-10 |
| 10761856 | Instruction completion table containing entries that share instruction tags | Kenneth L. Ward, Dung Q. Nguyen, Hung Q. Le | 2020-09-01 |
| 10740140 | Flush-recovery bandwidth in a processor | Steven J. Battle, Khandker N. Adeeb, Brian D. Barrick, Joshua W. Bowman, Brandon Goddard +2 more | 2020-08-11 |
| 10725786 | Completion mechanism for a microprocessor instruction completion table | Kenneth L. Ward, Dung Q. Nguyen, Glenn O. Kincaid, Joe Lee, Deepak Singh | 2020-07-28 |
| 10713057 | Mechanism to stop completions using stop codes in an instruction completion table | Kenneth L. Ward, Dung Q. Nguyen, Christopher M. Mueller, Joe Lee, Deepak Singh | 2020-07-14 |
| 10664275 | Speeding up younger store instruction execution after a sync instruction | Hung Q. Le, Bryan Lloyd, Dung Q. Nguyen, David Scott Ray, Benjamin W. Stolt +1 more | 2020-05-26 |
| 10552165 | Efficiently managing speculative finish tracking and error handling for load instructions | David A. Hrusecky, Christopher M. Mueller, Dung Q. Nguyen, A. James Van Norstrand, Jr., Kenneth L. Ward | 2020-02-04 |
| 10528347 | Executing system call vectored instructions in a multi-slice processor | Nicholas R. Orzol, Mehul Patel, Eula A. Tolentino | 2020-01-07 |
| 10423423 | Efficiently managing speculative finish tracking and error handling for load instructions | David A. Hrusecky, Christopher M. Mueller, Dung Q. Nguyen, A. James Van Norstrand, Jr., Kenneth L. Ward | 2019-09-24 |
| 10296339 | Thread transition management | Christopher M. Abernathy, Mary D. Brown, James Allan Kahle, Hung Q. Le, Dung Q. Nguyen | 2019-05-21 |
| 10289415 | Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data | Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry | 2019-05-14 |
| 10282205 | Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions | Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry | 2019-05-07 |
| 10255071 | Method and apparatus for managing a speculative transaction in a processing unit | Salma Ayub, Glenn O. Kincaid, Cliff Kucharski, Christopher M. Mueller, Dung Q. Nguyen +1 more | 2019-04-09 |
| 10073699 | Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture | Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry | 2018-09-11 |
| 10067765 | Speeding up younger store instruction execution after a sync instruction | Hung Q. Le, Bryan Lloyd, Dung Q. Nguyen, David Scott Ray, Benjamin W. Stolt +1 more | 2018-09-04 |
| 10055226 | Thread transition management | Christopher M. Abernathy, Mary D. Brown, James Allan Kahle, Hung Q. Le, Dung Q. Nguyen | 2018-08-21 |
| 10048963 | Executing system call vectored instructions in a multi-slice processor | Nicholas R. Orzol, Mehul Patel, Eula A. Tolentino | 2018-08-14 |
| 9971687 | Operation of a multi-slice processor with history buffers storing transaction memory state information | Brian D. Barrick, Kurt A. Feiste, Dung Q. Nguyen, Kenneth L. Ward, Jing Zhang | 2018-05-15 |
| 9703561 | Thread transition management | Christopher M. Abernathy, Mary D. Brown, James Allan Kahle, Hung Q. Le, Dung Q. Nguyen | 2017-07-11 |
| 9268599 | Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories | Robert J. Blainey, Harold W. Cain, III, Bradley G. Frey, Charles B. Hall, Hung Q. Le +1 more | 2016-02-23 |
| 9268598 | Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories | Robert J. Blainey, Harold W. Cain, III, Bradly G. Frey, Charles B. Hall, Hung Q. Le +1 more | 2016-02-23 |
| 8725993 | Thread transition management | Christopher M. Abernathy, Mary D. Brown, James Allan Kahle, Hung Q. Le, Dung Q. Nguyen | 2014-05-13 |
| 8386753 | Completion arbitration for more than two threads based on resource limitations | Dung Q. Nguyen, Balaram Sinharoy, Benjamin W. Stolt | 2013-02-26 |
| 8261276 | Power-efficient thread priority enablement | Pradip Bose, Alper Buyuktosunoglu, Richard J. Eickemeyer, Michael Stephen Floyd, Hans M. Jacobson +1 more | 2012-09-04 |
| 8131976 | Tracking effective addresses in an out-of-order processor | Richard W. Doing, David S. Levitan, Kevin N. Magill, Brian R. Mestan, Balaram Sinharoy +3 more | 2012-03-06 |