| 10664275 |
Speeding up younger store instruction execution after a sync instruction |
Susan E. Eisen, Hung Q. Le, Bryan Lloyd, Dung Q. Nguyen, David Scott Ray +1 more |
2020-05-26 |
| 10067765 |
Speeding up younger store instruction execution after a sync instruction |
Susan E. Eisen, Hung Q. Le, Bryan Lloyd, Dung Q. Nguyen, David Scott Ray +1 more |
2018-09-04 |
| 9495170 |
Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall |
Venkat R. Indukuru, Brian R. Konigsburg, Alexander Erik Mericas |
2016-11-15 |
| 9489207 |
Processor and method for partially flushing a dispatched instruction group including a mispredicted branch |
William E. Burky, Brian R. Mestan, Dung Q. Nguyen, Balaram Sinharoy |
2016-11-08 |
| 9389867 |
Speculative finish of instruction execution in a processor core |
Sundeep Chadha, Bryan Lloyd, Dung Q. Nguyen, David Scott Ray |
2016-07-12 |
| 9384002 |
Speculative finish of instruction execution in a processor core |
Sundeep Chadha, Bryan Lloyd, Dung Q. Nguyen, David Scott Ray |
2016-07-05 |
| 8874880 |
Instruction tracking system for processors |
Christopher M. Abernathy, Hung Q. Le, Dung Q. Nguyen |
2014-10-28 |
| 8635436 |
Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall |
Venkat R. Indukuru, Brian R. Konigsburg, Alexander Erik Mericas |
2014-01-21 |
| 8521998 |
Instruction tracking system for processors |
Christopher M. Abernathy, Hung Q. Le, Dung Q. Nguyen |
2013-08-27 |
| 8386753 |
Completion arbitration for more than two threads based on resource limitations |
Susan E. Eisen, Dung Q. Nguyen, Balaram Sinharoy |
2013-02-26 |
| 8131976 |
Tracking effective addresses in an out-of-order processor |
Richard W. Doing, Susan E. Eisen, David S. Levitan, Kevin N. Magill, Brian R. Mestan +3 more |
2012-03-06 |
| 7877580 |
Branch lookahead prefetch for microprocessors |
Richard J. Eickemeyer, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto |
2011-01-25 |
| 7779234 |
System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor |
James Wilson Bishop, Hung Q. Le, Dung Q. Nguyen, Wolfram Sauer, Michael Thomas Vaden |
2010-08-17 |
| 7620799 |
Using a modified value GPR to enhance lookahead prefetch |
Richard J. Eickemeyer, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto |
2009-11-17 |
| 7594096 |
Load lookahead prefetch for microprocessors |
Richard J. Eickemeyer, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto |
2009-09-22 |
| 7552318 |
Branch lookahead prefetch for microprocessors |
Richard J. Eickemeyer, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto |
2009-06-23 |
| 7444498 |
Load lookahead prefetch for microprocessors |
Richard J. Eickemeyer, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto |
2008-10-28 |
| 7421567 |
Using a modified value GPR to enhance lookahead prefetch |
Richard J. Eickemeyer, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto |
2008-09-02 |
