| 12072789 |
Resumable instruction generation |
Michael J. Brothers, Jingliang Wang, Noah Sherrill, Stephen Edwards |
2024-08-27 |
| 8099451 |
Systems and methods for implementing logic in a processor |
Fadi Y. Busaba, Bryan Lloyd |
2012-01-17 |
| 8024647 |
Method and system for checking rotate, shift and sign extension functions using a modulo function |
Fadi Y. Busaba, Lawrence Powell, Martin S. Schmookler, David A. Webber |
2011-09-20 |
| 7991816 |
Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units |
Brian W. Curran, Ashutosh Goyal, David A. Webber |
2011-08-02 |
| 7818550 |
Method and apparatus for dynamically fusing instructions at execution time in a processor of an information handling system |
— |
2010-10-19 |
| 7809924 |
System for generating effective address |
Rachel Flood, Scott Bruce Frommer, David A. Hrusecky, Sheldon B. Levenstein |
2010-10-05 |
| 7779234 |
System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor |
James Wilson Bishop, Hung Q. Le, Dung Q. Nguyen, Wolfram Sauer, Benjamin W. Stolt |
2010-08-17 |
| 7509365 |
Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units |
Brian W. Curran, Ashutosh Goyal, David A. Webber |
2009-03-24 |
| 7376890 |
Method and system for checking rotate, shift and sign extension functions using a modulo function |
Fadi Y. Busaba, Lawrence Powell, Martin S. Schmookler, David A. Webber |
2008-05-20 |
| 7360058 |
System and method for generating effective address |
Rachel Flood, Scott Bruce Frommer, David A. Hrusecky, Sheldon B. Levenstein |
2008-04-15 |
| 7051179 |
Method and system for supporting multiple cache configurations |
Keenan W. Franz |
2006-05-23 |
| 6914849 |
Method and apparatus for reducing power consumption in a memory array with dynamic word line driver/decoders |
Tai Anh Cao, Sam Gat-Shang Chu, Joseph J. McGill IV |
2005-07-05 |
| 6832329 |
Cache thresholding method, apparatus, and program for predictive reporting of array bit line or driver failures |
George Henry Ahrens, Alongkorn Kitamorn, Charles Andrew McLaughlin |
2004-12-14 |
| 6760272 |
Method and system for supporting multiple cache configurations |
Keenan W. Franz |
2004-07-06 |
| 6430680 |
Processor and method of prefetching data based upon a detected stride |
William E. Burky, David A. Schroter, Shih-Hsiung S. Tung |
2002-08-06 |
| 6401192 |
Apparatus for software initiated prefetch and method therefor |
David A. Schroter |
2002-06-04 |
| 6275918 |
Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold |
William E. Burky, Peter Steven Lenk, Dung Q. Nguyen, David A. Schroter, Shih-Hsiung S. Tung |
2001-08-14 |
| 6178493 |
Multiprocessor stalled store detection |
Peter Steven Lenk, Michael John Mayfield, Robert J. Reese |
2001-01-23 |
| 5822556 |
Distributed completion control in a microprocessor |
Terence M. Potter, Christopher H. Olson |
1998-10-13 |
| 5758119 |
System and method for indicating that a processor has prefetched data into a primary cache and not into a secondary cache |
Michael John Mayfield, Trinh Huy Nguyen, Robert J. Reese |
1998-05-26 |
| 5740399 |
Modified L1/L2 cache inclusion for aggressive prefetch |
Michael John Mayfield, Trinh Huy Nguyen, Robert J. Reese |
1998-04-14 |
