Issued Patents All Time
Showing 25 most recent of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11663315 | Just-in-time authentication | Chad Milito, Terrance Holbrook, Alan Rencher | 2023-05-30 |
| 11379228 | Microprocessor including an efficiency logic unit | Avraham Ayzenfeld, Lee Evan Eisen, Christian Jacobi | 2022-07-05 |
| 11223703 | Instruction initialization in a dataflow architecture | Bruce M. Fleischer, Kailash Gopalakrishnan, Sunil K. Shukla | 2022-01-11 |
| 11138010 | Loop management in multi-processor dataflow architecture | Chia-Yu Chen, Jungwook Choi, Bruce M. Fleischer, Kailash Gopalakrishnan, Jinwook Oh +2 more | 2021-10-05 |
| 10838868 | Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory components | Chia-Yu Chen, Jungwook Choi, Bruce M. Fleischer, Kailash Gopalakrishan, Jinwook Oh +3 more | 2020-11-17 |
| 10540183 | Accelerated execution of execute instruction target | Khary J. Alexander, Fadi Y. Busaba, David S. Hutton, Edward T. Malley, Brian R. Prasky +1 more | 2020-01-21 |
| 10514911 | Structure for microprocessor including arithmetic logic units and an efficiency logic unit | Avraham Ayzenfeld, Lee Evan Eisen, Christian Jacobi | 2019-12-24 |
| 10503503 | Generating design structure for microprocessor with arithmetic logic units and an efficiency logic unit | Avraham Ayzenfeld, Lee Evan Eisen, Christian Jacobi | 2019-12-10 |
| 10205623 | Custom event and attribute generation for use in website traffic data collection | Brett Michael Error, Chris Error | 2019-02-12 |
| 9875107 | Accelerated execution of execute instruction target | Khary J. Alexander, Fadi Y. Busaba, David S. Hutton, Edward T. Malley, Brian R. Prasky +1 more | 2018-01-23 |
| 9626293 | Single-thread cache miss rate estimation | James J. Bonanno, Alper Buyuktosunoglu, Willm Hinrichs, Christian Jacobi, Brian R. Prasky +4 more | 2017-04-18 |
| 9619385 | Single thread cache miss rate estimation | James J. Bonanno, Alper Buyuktosunoglu, Willm Hinrichs, Christian Jacobi, Brian R. Prasky +4 more | 2017-04-11 |
| 9575529 | Voltage droop reduction in a processor | Preetham M. Lobo, Richard F. Rizzolo, James D. Warnock, Tobias Webel | 2017-02-21 |
| 9430235 | Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors | Gregory W. Alexander, Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi, James R. Mitchell +2 more | 2016-08-30 |
| 9389865 | Accelerated execution of target of execute instruction | Khary J. Alexander, Fadi Y. Busaba, David S. Hutton, Edward T. Malley, Brian R. Prasky +1 more | 2016-07-12 |
| 9135005 | History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties | Khary J. Alexander, Fadi Y. Busaba, Bruce C. Giamei, Christian Jacobi, James R. Mitchell | 2015-09-15 |
| 9104399 | Dual issuing of complex instruction set instructions | Fadi Y. Busaba, Lee Evan Eisen, Christian Jacobi, David A. Schroter, Eric M. Schwarz | 2015-08-11 |
| 8645669 | Cracking destructively overlapping operands in variable length instructions | Khary J. Alexander, Fadi Y. Busaba, Bruce C. Giamei, Christian Jacobi | 2014-02-04 |
| 8521992 | Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors | Gregory W. Alexander, Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi, James R. Mitchell +2 more | 2013-08-27 |
| 8495341 | Instruction length based cracking for instruction of variable length storage operands | Fadi Y. Busaba, Bruce C. Giamei, Christian Jacobi, Wen H. Li | 2013-07-23 |
| 8468325 | Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors | Gregory W. Alexander, Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi, James R. Mitchell +2 more | 2013-06-18 |
| 8464030 | Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits | Fadi Y. Busaba, Lee Evan Eisen, Bruce C. Giamei, David S. Hutton | 2013-06-11 |
| 7991816 | Inverting data on result bus to prepare for instruction in the next cycle for high frequency execution units | Ashutosh Goyal, Michael Thomas Vaden, David A. Webber | 2011-08-02 |
| 7904697 | Load register instruction short circuiting method | Brian D. Barrick, Lee Evan Eisen | 2011-03-08 |
| 7676779 | Logic block timing estimation using conesize | Reinaldo A. Bergamaschi, Sean Michael Carey, Prabhakar Kudva, Matthew E. Mariani, Mark D. Mayo +1 more | 2010-03-09 |