Issued Patents All Time
Showing 25 most recent of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11112854 | Operating pulsed latches on a variable power supply | Steven M. Douskey, Raghu G. GopalaKrishnaSetty, Mary P. Kusko, Hari Krishnan Rajeev | 2021-09-07 |
| 11074391 | Characterizing and simulating library gates to enable identification and elimination of electromigration violations in semiconductor chips | Leon Sigal, David Kadzov, Nagashyamala R. Dhanwada | 2021-07-27 |
| 10678981 | Priority based circuit synthesis | Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan | 2020-06-09 |
| 10666415 | Determining clock signal quality using a plurality of sensors | Phillip J. Restle, Christos Vezyrtzis | 2020-05-26 |
| 10652006 | Determining clock signal quality using a plurality of sensors | Phillip J. Restle, Christos Vezyrtzis | 2020-05-12 |
| 10565336 | Pessimism reduction in cross-talk noise determination used in integrated circuit design | Jason D. Morsey, Steven E. Washburn, Patrick M. Williams | 2020-02-18 |
| 10386912 | Operating pulsed latches on a variable power supply | Steven M. Douskey, Raghu G. GopalaKrishnaSetty, Mary P. Kusko, Hari Krishnan Rajeev | 2019-08-20 |
| 10354046 | Programmable clock division methodology with in-context frequency checking | Naiju K. Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen +3 more | 2019-07-16 |
| 10288678 | Debugging scan latch circuits using flip devices | — | 2019-05-14 |
| 10216885 | Adjusting scan connections based on scan control locations | Raghu G. GopalaKrishnaSetty, Ankit N. Kagliwal, Sridhar H. Rangarajan | 2019-02-26 |
| 10191108 | On-chip sensor for monitoring active circuits on integrated circuit (IC) chips | Gregory G. Freeman, Siyuranga O. Koswatta, Paul S. McLaughlin, Daniel J. Poindexter, J. Campbell Scott +2 more | 2019-01-29 |
| 10133840 | Priority based circuit synthesis | Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan | 2018-11-20 |
| 10062709 | Programmable integrated circuit standard cell | Ayan Datta, Ankur Shukla | 2018-08-28 |
| 10002881 | Programmable integrated circuit standard cell | Ayan Datta, Ankur Shukla | 2018-06-19 |
| 9990454 | Early analysis and mitigation of self-heating in design flows | Nagashyamala R. Dhanwada, William W. Dungan, Arun Joseph, Sungjae Lee, Arjen A. Mets +3 more | 2018-06-05 |
| 9985616 | Programmable delay circuit including hybrid fin field effect transistors (finFETs) | Vijay K. Ankenapalli, Ayan Datta, Sumitha George, Charudhattan Nagarajan | 2018-05-29 |
| 9934348 | Adjusting scan connections based on scan control locations | Raghu G. GopalaKrishnaSetty, Ankit N. Kagliwal, Sridhar H. Rangarajan | 2018-04-03 |
| 9910954 | Programmable clock division methodology with in-context frequency checking | Naiju K. Abdul, Jennifer E. Basile, Hemlata Gupta, Kerim Kalafala, Jeremy J. Leitzen +3 more | 2018-03-06 |
| 9891276 | Performance-screen ring oscillator (PSRO) using an integrated circuit test signal distribution network | — | 2018-02-13 |
| 9762213 | Initializing scannable and non-scannable latches from a common clock buffer | William V. Huott, Ricardo H. Nigaglioni, Hagen Schmidt | 2017-09-12 |
| 9760664 | Validating variation of timing constraint measurements | Sachin Gupta, Vasant Rao, Suriya T. Skariah, James E. Sundquist | 2017-09-12 |
| 9760665 | Validating variation of timing constraint measurements | Sachin Gupta, Vasant Rao, Suriya T. Skariah, James E. Sundquist | 2017-09-12 |
| 9762212 | Initializing scannable and non-scannable latches from a common clock buffer | William V. Huott, Ricardo H. Nigaglioni, Hagen Schmidt | 2017-09-12 |
| 9720035 | Performance-screen ring oscillator (PSRO) using an integrated circuit test signal distribution network | — | 2017-08-01 |
| 9664735 | Debugging scan latch circuits using flip devices | — | 2017-05-30 |