Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11093675 | Statistical timing analysis considering multiple-input switching | Debjit Sinha, Michael H. Wood | 2021-08-17 |
| 10949593 | Model order reduction in transistor level timing | Robert J. Allen, Yanai Danan, Jeffrey P. Soreff, Xin Zhao | 2021-03-16 |
| 10394986 | Model order reduction in transistor level timing | Robert J. Allen, Yanai Danan, Jeffrey P. Soreff, Xin Zhao | 2019-08-27 |
| 10360329 | Multi-cycle signal identification for static timing analysis | Robert J. Allen, William J. Wright, Xin Zhao | 2019-07-23 |
| 10325059 | Incremental common path pessimism analysis | Tsung-Wei Huang, Kerim Kalafala, Debjit Sinha, Natesan Venkateswaran | 2019-06-18 |
| 10031988 | Model order reduction in transistor level timing | Robert J. Allen, Yanai Danan, Jeffrey P. Soreff, Xin Zhao | 2018-07-24 |
| 9836572 | Incremental common path pessimism analysis | Tsung-Wei Huang, Kerim Kalafala, Debjit Sinha, Natesan Venkateswaran | 2017-12-05 |
| 9785737 | Parallel multi-threaded common path pessimism removal in multiple paths | David J. Hathaway, Kerim Kalafala, Alexander J. Suess, Vladimir Zolotov | 2017-10-10 |
| 9760664 | Validating variation of timing constraint measurements | Sachin Gupta, Suriya T. Skariah, James E. Sundquist, James D. Warnock | 2017-09-12 |
| 9760665 | Validating variation of timing constraint measurements | Sachin Gupta, Suriya T. Skariah, James E. Sundquist, James D. Warnock | 2017-09-12 |
| 9690899 | Prioritized path tracing in statistical timing analysis of integrated circuits | Debjit Sinha, Chandramouli Visweswariah | 2017-06-27 |
| 9659121 | Deterministic and statistical timing modeling for differential circuits | Hemlata Gupta, Jin Hu, Chad Andrew Marquart, Debjit Sinha | 2017-05-23 |
| 9613171 | Multi-cycle signal identification for static timing analysis | Robert J. Allen, William J. Wright, Xin Zhao | 2017-04-04 |
| 9501608 | Timing analysis of circuits using sub-circuit timing models | Robert J. Allen, Yanai Danan, Xin Zhao | 2016-11-22 |
| 8776004 | Method for improving static timing analysis and optimizing circuits using reverse merge | Frank Borkam, Hemlata Gupta, David J. Hathaway, Kerim Kalafala, Alex Rubin | 2014-07-08 |
| 8655634 | Modeling loading effects of a transistor network | David J. Hathaway, Ronald D. Rose, Ali Sadigh, Jeffrey P. Soreff, David W. Winston | 2014-02-18 |
| 8201120 | Timing point selection for a static timing analysis in the presence of interconnect electrical elements | Jeffrey P. Soreff, Barry Lee Dorfman, Jeffrey G. Hemmett, Ravichander Ledalla, Fred Yang | 2012-06-12 |
| 8112735 | Affinity-based clustering of vectors for partitioning the columns of a matrix | Kerim Kalafala, Chandramouli Visweswariah | 2012-02-07 |
| 7958484 | Affinity-based clustering of vectors for partitioning the columns of a matrix | Kerim Kalafala, Chandramouli Visweswariah | 2011-06-07 |
| 7870515 | System and method for improved hierarchical analysis of electronic circuits | Philip G. Shephard, III, Ravichander Ledalla, Jeffrey P. Soreff | 2011-01-11 |
| 7643981 | Pulse waveform timing in EinsTLT templates | Sang-Yeol Lee, Jeffrey P. Soreff, James D. Warnock, David W. Winston | 2010-01-05 |
| 7353359 | Affinity-based clustering of vectors for partitioning the columns of a matrix | Kerim Kalafala, Chandramouli Visweswariah | 2008-04-01 |
| 7325210 | Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect | Cindy S. Washburn, Jun Zhou, Jeffrey P. Soreff, Patrick M. Williams, David J. Hathaway | 2008-01-29 |
| 6763504 | Method for reducing RC parasitics in interconnect networks of an integrated circuit | Ravichander Ledalla, Jeffrey P. Soreff, Fred Yang | 2004-07-13 |