| 10949593 |
Model order reduction in transistor level timing |
Robert J. Allen, Yanai Danan, Vasant Rao, Xin Zhao |
2021-03-16 |
| 10394986 |
Model order reduction in transistor level timing |
Robert J. Allen, Yanai Danan, Vasant Rao, Xin Zhao |
2019-08-27 |
| 10031988 |
Model order reduction in transistor level timing |
Robert J. Allen, Yanai Danan, Vasant Rao, Xin Zhao |
2018-07-24 |
| 8655634 |
Modeling loading effects of a transistor network |
David J. Hathaway, Vasant Rao, Ronald D. Rose, Ali Sadigh, David W. Winston |
2014-02-18 |
| 8607176 |
Delay model construction in the presence of multiple input switching events |
Bhavana Agrawal, David J. Hathaway |
2013-12-10 |
| 8201120 |
Timing point selection for a static timing analysis in the presence of interconnect electrical elements |
Barry Lee Dorfman, Jeffrey G. Hemmett, Ravichander Ledalla, Vasant Rao, Fred Yang |
2012-06-12 |
| 8141014 |
System and method for common history pessimism relief during static timing analysis |
Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Kerim Kalafala |
2012-03-20 |
| 8108816 |
Device history based delay variation adjustment during static timing analysis |
Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey G. Hemmett, Kerim Kalafala |
2012-01-31 |
| 7870515 |
System and method for improved hierarchical analysis of electronic circuits |
Philip G. Shephard, III, Ravichander Ledalla, Vasant Rao |
2011-01-11 |
| 7643981 |
Pulse waveform timing in EinsTLT templates |
Sang-Yeol Lee, Vasant Rao, James D. Warnock, David W. Winston |
2010-01-05 |
| 7552040 |
Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects |
Barry Lee Dorfman, Thomas E. Rosser |
2009-06-23 |
| 7325210 |
Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect |
Vasant Rao, Cindy S. Washburn, Jun Zhou, Patrick M. Williams, David J. Hathaway |
2008-01-29 |
| 7225419 |
Methods for modeling latch transparency |
Erwin Behnen, James D. Warnock, Dieter Wendel |
2007-05-29 |
| 7191419 |
Method of timing model abstraction for circuits containing simultaneously switching internal signals |
James D. Warnock |
2007-03-13 |
| 7080335 |
Methods for modeling latch transparency |
Erwin Behnen, James D. Warnock, Dieter Wendel |
2006-07-18 |
| 6763504 |
Method for reducing RC parasitics in interconnect networks of an integrated circuit |
Vasant Rao, Ravichander Ledalla, Fred Yang |
2004-07-13 |
| 6718523 |
Reduced pessimism clock gating tests for a timing analysis tool |
David J. Hathaway, Neil Ray Vanderschaaf, James D. Warnock |
2004-04-06 |
| 6430731 |
Methods and apparatus for performing slew dependent signal bounding for signal timing analysis |
Jin-Fuw Lee, Daniel L. Ostapko, Chak-Kuen Wong |
2002-08-06 |
| 5365463 |
Method for evaluating the timing of digital machines with statistical variability in their delays |
Wilm E. Donath, Robert B. Hitchcock |
1994-11-15 |
