Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7047163 | Method and apparatus for applying fine-grained transforms during placement synthesis interaction | Kanad Chakraborty, Prabhakar Kudva, Lakshmi N. Reddy, Leon Stok, Andrew J. Sullivan +1 more | 2006-05-16 |
| 6738954 | Method for prediction random defect yields of integrated circuits with accuracy and computation time controls | Archibald J. Allen, Alan Dziedzic, Mark A. Lavin, Daniel N. Maynard, Dennis M. Newns +1 more | 2004-05-18 |
| 6557151 | Distributed static timing analysis | David J. Hathaway | 2003-04-29 |
| 6314547 | Method for improving the assignment of circuit locations during fabrication | Prabhakar Kudva | 2001-11-06 |
| 6274916 | Ultrafast nanoscale field effect transistor | Dennis M. Newns, Pratap C. Pattnaik | 2001-08-14 |
| 6202192 | Distributed static timing analysis | David J. Hathaway | 2001-03-13 |
| 5761488 | Logic translation method for increasing simulation emulation efficiency | Helmut Roth | 1998-06-02 |
| 5392221 | Procedure to minimize total power of a logic network subject to timing constraints | Wing K. Luk, Donald T. Tang | 1995-02-21 |
| 5365463 | Method for evaluating the timing of digital machines with statistical variability in their delays | Robert B. Hitchcock, Jeffrey P. Soreff | 1994-11-15 |
| 5218551 | Timing driven placement | Bhuwan Agrawal, Stephen E. Bello, San Y. Han, Joseph Hutt, Jr., Jerome M. Kurtzberg +4 more | 1993-06-08 |
| 4263651 | Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks | Robert B. Hitchcock | 1981-04-21 |