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Method and apparatus for applying fine-grained transforms during placement synthesis interaction |
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Method for prediction random defect yields of integrated circuits with accuracy and computation time controls |
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| 6557151 |
Distributed static timing analysis |
David J. Hathaway |
2003-04-29 |
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Method for improving the assignment of circuit locations during fabrication |
Prabhakar Kudva |
2001-11-06 |
| 6274916 |
Ultrafast nanoscale field effect transistor |
Dennis M. Newns, Pratap C. Pattnaik |
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Distributed static timing analysis |
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2001-03-13 |
| 5761488 |
Logic translation method for increasing simulation emulation efficiency |
Helmut Roth |
1998-06-02 |
| 5392221 |
Procedure to minimize total power of a logic network subject to timing constraints |
Wing K. Luk, Donald T. Tang |
1995-02-21 |
| 5365463 |
Method for evaluating the timing of digital machines with statistical variability in their delays |
Robert B. Hitchcock, Jeffrey P. Soreff |
1994-11-15 |
| 5218551 |
Timing driven placement |
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Method for determining the characteristics of a logic block graph diagram to provide an indication of path delays between the blocks |
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