Issued Patents All Time
Showing 25 most recent of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12008150 | Encrypted data processing design including cleartext register files | Jessica Hui-Chun Tseng, Jose E. Moreira, Manoj Kumar, Kattamuri Ekanadham, Gianfranco Bilardi | 2024-06-11 |
| 11900116 | Loosely-coupled slice target file data | Dung Q. Nguyen, Brian W. Thompto, Jose E. Moreira, Jessica Hui-Chun Tseng, Kattamuri Ekanadham +1 more | 2024-02-13 |
| 11868275 | Encrypted data processing design including local buffers | Manoj Kumar, Gianfranco Bilardi, Kattamuri Ekanadham, Jose E. Moreira, Jessica Hui-Chun Tseng | 2024-01-09 |
| 11836493 | Memory access operations for large graph analytics | Manoj Kumar, Gianfranco Bilardi, Kattamuri Ekanadham, Jose E. Moreira, Jessica Hui-Chun Tseng | 2023-12-05 |
| 11663009 | Supporting large-word operations in a reduced instruction set computer (“RISC”) processor | Sandhya Koteshwara, Kattamuri Ekanadham, Manoj Kumar, Jose E. Moreira | 2023-05-30 |
| 11294685 | Instruction fusion using dependence analysis | Jessica Hui-Chun Tseng, Manoj Kumar, Kattamuri Ekanadham, Jose E. Moreira | 2022-04-05 |
| 11163528 | Reformatting matrices to improve computing efficiency | Manoj Kumar, Kattamuri Ekanadham, Jessica Hui-Chun Tseng, Jose E. Moreira | 2021-11-02 |
| 11080037 | Software patch management incorporating sentiment analysis | Kaoutar El Maghraoui, Joefon Jann, Clifford A. Pickover | 2021-08-03 |
| 10984073 | Dual phase matrix-vector multiplication system | Mauricio J. Serrano, Manoj Kumar | 2021-04-20 |
| 10956361 | Processor core design optimized for machine learning applications | Manoj Kumar, Kattamuri Ekanadham, Jessica Hui-Chun Tseng, Jose E. Moreira | 2021-03-23 |
| 10956167 | Mechanism for instruction fusion using tags | Jessica Hui-Chun Tseng, Manoj Kumar, Kattamuri Ekanadham, Jose E. Moreira | 2021-03-23 |
| 10949202 | Identifying and tracking frequently accessed registers in a processor | Jessica Hui-Chun Tseng | 2021-03-16 |
| 10936320 | Efficient performance of inner loops on a multi-lane processor | Kattamuri Ekanadham, Manoj Kumar, Jose E. Moreira, Jessica Hui-Chun Tseng | 2021-03-02 |
| 10884942 | Reducing memory access latency in scatter/gather operations | William P. Horn, Joefon Jann, Manoj Kumar, Jose E. Moreira, Mauricio J. Serrano +1 more | 2021-01-05 |
| 10802971 | Cache memory transaction shielding via prefetch suppression | Harold W. Cain, III | 2020-10-13 |
| 10684959 | Shared memory in a virtual environment | Ramanjaneya Sarma Burugula, Niteesh K. Dubey, Joefon Jann, Hao Yu | 2020-06-16 |
| 10546121 | Security within a software-defined infrastructure | Brad L. Brech, Scott W. Crowder, Hubertus Franke, Nagui Halim, Matt R. Hogstrom +5 more | 2020-01-28 |
| 10534911 | Security within a software-defined infrastructure | Brad L. Brech, Scott W. Crowder, Hubertus Franke, Nagui Halim, Matt R. Hogstrom +5 more | 2020-01-14 |
| 10423457 | Outcome-based software-defined infrastructure | Brad L. Brech, Scott W. Crowder, Hubertus Franke, Jeffrey A. Frey, Nagui Halim +8 more | 2019-09-24 |
| 10417304 | Dual phase matrix-vector multiplication system | Mauricio J. Serrano, Manoj Kumar | 2019-09-17 |
| 10365825 | Invalidation of shared memory in a virtual environment | Ramanjaneya Sarma Burugula, Niteesh K. Dubey, Joefon Jann, Hao Yu | 2019-07-30 |
| 10216544 | Outcome-based software-defined infrastructure | Brad L. Brech, Scott W. Crowder, Hubertus Franke, Jeffrey A. Frey, Nagui Halim +8 more | 2019-02-26 |
| 10209889 | Invalidation of shared memory in a virtual environment | Ramanjaneya Sarma Burugula, Niteesh K. Dubey, Joefon Jann, Hao Yu | 2019-02-19 |
| 10176115 | Shared memory in a virtual environment | Ramanjaneya Sarma Burugula, Niteesh K. Dubey, Joefon Jann, Hao Yu | 2019-01-08 |
| 10114632 | Software patch management incorporating sentiment analysis | Kaoutar El Maghraoui, Joefon Jann, Clifford A. Pickover | 2018-10-30 |