Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10546121 | Security within a software-defined infrastructure | Brad L. Brech, Hubertus Franke, Nagui Halim, Matt R. Hogstrom, Chung-Sheng Li +5 more | 2020-01-28 |
| 10534911 | Security within a software-defined infrastructure | Brad L. Brech, Hubertus Franke, Nagui Halim, Matt R. Hogstrom, Chung-Sheng Li +5 more | 2020-01-14 |
| 10423457 | Outcome-based software-defined infrastructure | Brad L. Brech, Hubertus Franke, Jeffrey A. Frey, Nagui Halim, Matt R. Hogstrom +8 more | 2019-09-24 |
| 10216544 | Outcome-based software-defined infrastructure | Brad L. Brech, Hubertus Franke, Jeffrey A. Frey, Nagui Halim, Matt R. Hogstrom +8 more | 2019-02-26 |
| 10043007 | Security within a software-defined infrastructure | Brad L. Brech, Hubertus Franke, Nagui Halim, Matt R. Hogstrom, Chung-Sheng Li +5 more | 2018-08-07 |
| 9851933 | Capability-based abstraction of software-defined infrastructure | Brad L. Brech, Hubertus Franke, Jeffrey A. Frey, Nagui Halim, Matt R. Hogstrom +11 more | 2017-12-26 |
| 9729421 | Outcome-based software-defined infrastructure | Brad L. Brech, Hubertus Franke, Jeffrey A. Frey, Nagui Halim, Matt R. Hogstrom +8 more | 2017-08-08 |
| 9652612 | Security within a software-defined infrastructure | Brad L. Brech, Hubertus Franke, Nagui Halim, Matt R. Hogstrom, Chung-Sheng Li +5 more | 2017-05-16 |
| 7098676 | Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor | William Francis Landers, Thomas M. Shaw, Diana Llera-Hurlburt, Vincent J. McGahay, Sandra G. Malhotra +3 more | 2006-08-29 |
| 6884734 | Vapor phase etch trim structure with top etch blocking layer | Frederick Buehrer, Derek Chen, William Chu, Sadanand V. Deshpande, David V. Horak +4 more | 2005-04-26 |
| 6686617 | Semiconductor chip having both compact memory and high performance logic | Paul D. Agnello, Bomy Chen, Ramachandra Divakaruni, Subramanian S. Iyer, Dennis Sinitsky | 2004-02-03 |
| 6395587 | Fully amorphized source/drain for leaky junctions | Dominic J. Schepis, Melanie J. Sherony | 2002-05-28 |
| 6372559 | Method for self-aligned vertical double-gate MOSFET | Michael Hargrove, Suk Hoon Ku, L. Ronald Logan | 2002-04-16 |
| 6369434 | Nitrogen co-implantation to form shallow junction-extensions of p-type metal oxide semiconductor field effect transistors | Kai CK Chen, Liang Han, Michael Hargrove, Kam-Leung Lee, Hung Y. Ng | 2002-04-09 |
| 6335262 | Method for fabricating different gate oxide thicknesses within the same chip | Anthony G. Domenicucci, Liang Han, Michael Hargrove, Paul A. Ronsheim | 2002-01-01 |
| 6287913 | Double polysilicon process for providing single chip high performance logic and compact embedded memory structure | Paul D. Agnello, Bomy Chen, Ramachandra Divakaruni, Subramanian S. Iyer, Dennis Sinitsky | 2001-09-11 |
| 6261876 | Planar mixed SOI-bulk substrate for microelectronic applications | Robert Hannon, Subramanian S. Iyer | 2001-07-17 |