Issued Patents All Time
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8227792 | Relaxed low-defect SGOI for strained SI CMOS applications | Stephen W. Bedell, Robert H. Dennard, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana | 2012-07-24 |
| 7993990 | Multiple crystallographic orientation semiconductor structures | Shreesh Narasimha, Xiaomeng Chen, Judson R. Holt, Mukesh V. Khare, Byeong Y. Kim +1 more | 2011-08-09 |
| 7696573 | Multiple crystallographic orientation semiconductor structures | Shreesh Narasimha, Xiaomeng Chen, Judson R. Holt, Mukesh V. Khare, Byeong Y. Kim +1 more | 2010-04-13 |
| 7683434 | Preventing cavitation in high aspect ratio dielectric regions of semiconductor device | Rajeev Malik, K. Paul Muller | 2010-03-23 |
| 7459384 | Preventing cavitation in high aspect ratio dielectric regions of semiconductor device | Rajeev Malik, K. Paul Muller | 2008-12-02 |
| 7361556 | Method of fabricating semiconductor side wall fin | James W. Adkisson, Arne Ballantine, Rama Divakaruni, Erin C. Jones, Edward J. Nowak +1 more | 2008-04-22 |
| 7358166 | Relaxed, low-defect SGOI for strained Si CMOS applications | Stephen W. Bedell, Robert H. Dennard, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana | 2008-04-15 |
| 7265417 | Method of fabricating semiconductor side wall fin | James W. Adkisson, Arne Ballantine, Rama Divakaruni, Erin C. Jones, Edward J. Nowak +1 more | 2007-09-04 |
| 7163864 | Method of fabricating semiconductor side wall fin | James W. Adkisson, Arne Ballantine, Rama Divakaruni, Erin C. Jones, Edward J. Nowak +1 more | 2007-01-16 |
| 7112845 | Double gate trench transistor | James W. Adkisson, Arne Ballantine, Rama Divakaruni, Erin C. Jones, Jed H. Rankin | 2006-09-26 |
| 7081676 | Structure for controlling the interface roughness of cobalt disilicide | Cyril Cabral, Jr., Roy A. Carruthers, James M. E. Harper, Christian Lavoie, Kirk D. Peterson +4 more | 2006-07-25 |
| 6946373 | Relaxed, low-defect SGOI for strained Si CMOS applications | Stephen W. Bedell, Robert H. Dennard, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana | 2005-09-20 |
| 6916729 | Salicide formation method | Sunfei Fang, Keith Kwong Hon Wong, Christian Lavoie, Lawrence A. Clevenger, Chester T. Dziobkowski +4 more | 2005-07-12 |
| 6891228 | CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture | Heemyong Park, Byoung Hun Lee, Dominic J. Schepis, Ghavam G. Shahidi | 2005-05-10 |
| 6828630 | CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture | Heemyong Park, Byoung Hun Lee, Dominic J. Schepis, Ghavam G. Shahidi | 2004-12-07 |
| 6809030 | Method and structure for controlling the interface roughness of cobalt disilicide | Cyril Cabral, Jr., Roy A. Carruthers, James M. E. Harper, Christian Lavoie, Kirk D. Peterson +4 more | 2004-10-26 |
| 6686617 | Semiconductor chip having both compact memory and high performance logic | Bomy Chen, Scott W. Crowder, Ramachandra Divakaruni, Subramanian S. Iyer, Dennis Sinitsky | 2004-02-03 |
| 6593660 | Plasma treatment to enhance inorganic dielectric adhesion to copper | Leena Paivikki Buchwalter, Barbara Luther, John P. Hummel, Terence L. Kane, Dirk Manger +3 more | 2003-07-15 |
| 6563131 | Method and structure of a dual/wrap-around gate field effect transistor | James W. Adkisson, Arne Ballantine, Christopher S. Putnam, Jed H. Rankin | 2003-05-13 |
| 6472258 | Double gate trench transistor | James W. Adkisson, Arne Ballantine, Rama Divakaruni, Erin C. Jones, Jed H. Rankin | 2002-10-29 |
| 6440851 | Method and structure for controlling the interface roughness of cobalt disilicide | Cyril Cabral, Jr., Roy A. Carruthers, James M. E. Harper, Christian Lavoie, Kirk D. Peterson +4 more | 2002-08-27 |
| 6406962 | Vertical trench-formed dual-gate FET device structure and method for creation | Arne Ballantine, Ramachandra Divakaruni, Erin C. Jones, Edward J. Nowak, Jed H. Rankin | 2002-06-18 |
| 6407436 | Semiconductor device with abrupt source/drain extensions with controllable gate electrode overlap | Peter Smeys | 2002-06-18 |
| 6287913 | Double polysilicon process for providing single chip high performance logic and compact embedded memory structure | Bomy Chen, Scott W. Crowder, Ramachandra Divakaruni, Subramanian S. Iyer, Dennis Sinitsky | 2001-09-11 |
| 6274446 | Method for fabricating abrupt source/drain extensions with controllable gate electrode overlap | Peter Smeys | 2001-08-14 |