Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
RM

Rajeev Malik — 26 Patents

IBM: 21 patents #5,188 of 70,183Top 8%
Infineon Technologies Ag: 9 patents #1,028 of 7,486Top 15%
Google: 1 patents #14,887 of 22,993Top 65%
Pleasantville, NY: #22 of 229 inventorsTop 10%
New York: #4,926 of 115,490 inventorsTop 5%
Overall (All Time): #150,017 of 4,157,543Top 4%
26 Patents All Time
Rajeev Malik has been granted 26 US patents while listed as an inventor at IBM. The first was granted in 2001 and the most recent in May 2014. Rajeev Malik ranks #150,017 of 4,157,543 US inventors in our database (top 3.6%). Patent records list Rajeev Malik in Pleasantville, NY, US.

Patents per Year

Patents granted per year, 2001 to 2014Bar chart with a peak of 5 patents in 2004.peak 52001: 1 patents20012002: 1 patents2003: 4 patents20032004: 5 patents2005: 2 patents20052006: 2 patents2007: 1 patents20072008: 4 patents2009: 1 patents20092010: 3 patents2011: 1 patents20112014: 1 patents2014

Issued Patents All Time

Showing 1–25 of 26 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8725597 Merchant scoring system and transactional database Michael Jon Mauseth, Woodrow Arnold Jones, Jr., Joel R. Springer 2014-05-13 $16,719,000
7928571 Device having dual etch stop liner and reformed silicide layer and related methods Dureseti Chidambarrao, Ying Li, Shreesh Narasimha 2011-04-19 $4,236,000
7776695 Semiconductor device structure having low and high performance devices of same conductive type on same substrate John C. Arnold, Dureseti Chidambarrao, Ying Li, Shreesh Narasimha, Siddhartha Panda +2 more 2010-08-17 $4,695,000
7732270 Device having enhanced stress state and related methods Dureseti Chidambarrao, Ying Li, Shreesh Narasimha, Haining Yang, Huilong Zhu 2010-06-08 $3,517,000
7683434 Preventing cavitation in high aspect ratio dielectric regions of semiconductor device Paul D. Agnello, K. Paul Muller 2010-03-23 $4,775,000
7627836 OPC trimming for performance James A. Culp, Lars Liebmann, K. Paul Muller, Shreesh Narasimha, Stephen L. Runyon +1 more 2009-12-01 $16,004,000
7459384 Preventing cavitation in high aspect ratio dielectric regions of semiconductor device Paul D. Agnello, K. Paul Muller 2008-12-02 $5,263,000
7446062 Device having dual etch stop liner and reformed silicide layer and related methods Dureseti Chidambarrao, Ying Li, Shreesh Narasimha 2008-11-04 $6,466,000
7446395 Device having dual etch stop liner and protective layer Dureseti Chidambarrao, Ying Li, Shreesh Narasimha 2008-11-04 $6,466,000
7348635 Device having enhanced stress state and related methods Dureseti Chidambarrao, Ying Li, Shreesh Narasimha, Haining Yang, Huilong Zhu 2008-03-25 $5,860,000
7306983 Method for forming dual etch stop liner and protective layer in a semiconductor device Dureseti Chidambarrao, Ying Li, Shreesh Narasimha 2007-12-11 $7,826,000
7030012 Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM Ramachandra Divakaruni, Oleg Gluschenkov, Oh-Jung Kwon 2006-04-18 $9,074,000
7018779 Apparatus and method to improve resist line roughness in semiconductor wafer processing Wai-Kin Li, Joseph J. Mezzapelle 2006-03-28 $16,084,000
6908806 Gate metal recess for oxidation protection and parasitic capacitance reduction Haining Yang, Ramachandra Divakaruni, Oleg Gluschenkov, Hongwen Yan, Ravikumar Ramachandran 2005-06-21
6897107 Method for forming TTO nitride liner for improved collar protection and TTO reliability Rama Divakaruni, Thomas W. Dyer, Jack A. Mandelman, Venkatachajam C. Jaiprakash 2005-05-24
6809368 TTO nitride liner for improved collar protection and TTO reliability Rama Divakaruni, Thomas W. Dyer, Jack A. Mandelman, Venkatachalam C. Jaiprakash 2004-10-26 $17,835,000
6794242 Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts Thomas W. Dyer, Andreas Knorr, Laertis Economikos, Scott D. Halle, Norbert Arnod 2004-09-21
6794282 Three layer aluminum deposition process for high aspect ratio CL contacts Thomas Goebel, Werner Robl, Mihel Seitz 2004-09-21 $92,000
6790739 Structure and methods for process integration in vertical DRAM cell fabrication Larry Nesbit, Jochen Beintner, Rama Divakaruni 2004-09-14 $5,712,000
6724054 Self-aligned contact formation using double SiN spacers Woo-Tag Kang, Mihel Seitz 2004-04-20 $84,000
6635526 Structure and method for dual work function logic devices in vertical DRAM process Rama Divakaruni, Rajesh Rengarajan 2003-10-21 $216,000
6620676 Structure and methods for process integration in vertical DRAM cell fabrication Larry Nesbit, Jochen Beintner, Rama Divakaruni 2003-09-16 $13,659,000
6541810 Modified vertical MOSFET and methods of formation thereof Ramachandra Divakaruni, Prakash Dev, Larry Nesbit 2003-04-01 $11,931,000
6509226 Process for protecting array top oxide Venkatachalam C. Jaiprakash, Jack A. Mandelman, Ramachandra Divakaruni, Mihel Seitz 2003-01-21
6358867 Orientation independent oxidation of silicon Helmut Tews, Jonathan E. Faltermeir, Carol J. Heenan, Oleg Gluschenkov 2002-03-19