Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6960523 | Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device | Michael Maldei, David M. Dobuzinsky, Johnathan E. Faltermeier, Thomas Rupp, Chienfan Yu +3 more | 2005-11-01 |
| 6740539 | Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates | Richard A. Conti, David M. Dobuzinsky, Daniel C. Edelstein, Gill Yong Lee, Kia-Seng Low +3 more | 2004-05-25 |
| 6649531 | Process for forming a damascene structure | William J. Cote, Timothy J. Dalton, Daniel C. Edelstein, Scott D. Halle, Gill Yong Lee +1 more | 2003-11-18 |
| 6620699 | Method for forming inside nitride spacer for deep trench device DRAM cell | Arnd Scholz | 2003-09-16 |
| 6570256 | Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates | Richard A. Conti, David M. Dobuzinsky, Daniel C. Edelstein, Gill Yong Lee, Kia-Seng Low +3 more | 2003-05-27 |
| 6541810 | Modified vertical MOSFET and methods of formation thereof | Ramachandra Divakaruni, Rajeev Malik, Larry Nesbit | 2003-04-01 |