Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JC

James A. Culp — 50 Patents

IBM: 44 patents #2,053 of 70,183Top 3%
Globalfoundries: 3 patents #1,029 of 4,424Top 25%
MGMentor Graphics: 2 patents #191 of 698Top 30%
Newburgh, NY: #7 of 198 inventorsTop 4%
New York: #1,879 of 115,490 inventorsTop 2%
Overall (All Time): #53,743 of 4,157,543Top 2%
50 Patents All Time
James A. Culp has been granted 50 US patents while listed as an inventor at IBM. The first was granted in 2002 and the most recent in February 2018. James A. Culp ranks #53,743 of 4,157,543 US inventors in our database (top 1.3%). Patent records list James A. Culp in Newburgh, NY, US.

Patents per Year

Patents granted per year, 2002 to 2018Bar chart with a peak of 10 patents in 2012.peak 102002: 1 patents20022003: 1 patents2004: 2 patents20042005: 1 patents2006: 1 patents20062007: 1 patents2008: 1 patents20082009: 5 patents2010: 3 patents20102011: 6 patents2012: 10 patents20122013: 8 patents2015: 3 patents20152016: 5 patents2017: 1 patents20172018: 1 patents2018

Issued Patents All Time

Showing 1–25 of 50 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9898573 Rule and process assumption co-optimization using feature-specific layout-based statistical analyses Chieh-Yu Lin, Dongbing Shao 2018-02-20 $9,359,000
9836570 Semiconductor layout generation Atsushi Azuma, Yuping Cui, Marco Facchini, Shaoning Yao 2017-12-05 $14,904,000
9455186 Selective local metal cap layer formation for improved electromigration behavior Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, Thomas W. Dyer +4 more 2016-09-27 $4,099,000
9406560 Selective local metal cap layer formation for improved electromigration behavior Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, Thomas W. Dyer +4 more 2016-08-02 $5,615,000
9385038 Selective local metal cap layer formation for improved electromigration behavior Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, Thomas W. Dyer +4 more 2016-07-05 $5,294,000
9311443 Correcting for stress induced pattern shifts in semiconductor manufacturing Dureseti Chidambarrao, Paul C. Parries, Ian P. Stobert 2016-04-12
9311442 Net-voltage-aware optical proximity correction (OPC) Shayak Banerjee, Ian P. Stobert 2016-04-12 $1,143,000
9076847 Selective local metal cap layer formation for improved electromigration behavior Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, Thomas W. Dyer +4 more 2015-07-07 $5,899,000
9075106 Detecting chip alterations with light emission Kerry Bernstein, David F. Heidel, Dirk Pfeiffer, Anthony D. Polson, Peilin Song +2 more 2015-07-07 $5,899,000
8997028 Methods and system for analysis and management of parametric yield Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason D. Hibbeler, Anda C. Mocuta 2015-03-31 $6,306,000
8473885 Physical design system and method John M. Cohn, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin, Jin-Fuw Lee +6 more 2013-06-25 $6,528,000
8470713 Nitride etch for improved spacer uniformity John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin, Christa R. Willets 2013-06-25 $6,528,000
8458625 Yield enhancement by multiplicate-layer-handling optical correction Pavan Y. Bashaboina 2013-06-04 $4,195,000
8429576 Methods and system for analysis and management of parametric yield Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason D. Hibbeler, Anda C. Mocuta 2013-04-23 $12,549,000
8418087 Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance Shayak Banerjee, Dureseti Chidambarrao, Praveen Elakkumanan, Saibal Mukhopadhyay 2013-04-09 $4,611,000
8381141 Method and system for comparing lithographic processing conditions and or data preparation processes Stephen E. Fischer, Robert T. Sayah 2013-02-19 $3,959,000
8347260 Method of designing an integrated circuit based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage Kerry Bernstein, Leah M. P. Pastel, Kirk D. Peterson, Norman J. Rohrer 2013-01-01
8347259 Circuit enhancement by multiplicate-layer-handling circuit simulation Pavan Y. Bashaboina 2013-01-01
8336008 Characterization of long range variability Jerry D. Hayes, Ying Liu, Anthony D. Polson 2012-12-18 $19,488,000
8301290 System and method for correcting systematic parametric variations on integrated circuit chips in order to minimize circuit limited yield loss John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin 2012-10-30
8302068 Leakage aware design post-processing Lars Liebmann 2012-10-30
8239790 Methods and system for analysis and management of parametric yield Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason D. Hibbeler, Anda C. Mocuta 2012-08-07 $7,112,000
8232215 Spacer linewidth control Jeffrey P. Gambino, John J. Ellis-Monaghan, Kirk D. Peterson, Jed H. Rankin 2012-07-31 $5,473,000
8219943 Physical design system and method John M. Cohn, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin, Jin-Fuw Lee +6 more 2012-07-10 $6,782,000
8214770 Multilayer OPC for design aware manufacturing Maharaj Mukherjee, Lars Liebmann, Scott M. Mansfield 2012-07-03 $4,930,000