JH

Jerry D. Hayes

IBM: 33 patents #2,996 of 70,183Top 5%
Overall (All Time): #108,580 of 4,157,543Top 3%
33
Patents All Time

Issued Patents All Time

Showing 25 most recent of 33 patents

Patent #TitleCo-InventorsDate
8862426 Method and test system for fast determination of parameter variation statistics Kanak B. Agarwal, Sani R. Nassif 2014-10-14
8676516 Test circuit for bias temperature instability recovery measurements Fadi H. Gebara, John P. Keane, Sani R. Nassif, Jeremy D. Schaub 2014-03-18
8336008 Characterization of long range variability James A. Culp, Ying Liu, Anthony D. Polson 2012-12-18
8229683 Test circuit for bias temperature instability recovery measurements Fadi H. Gebara, John P. Keane, Sani R. Nassif, Jeremy D. Schaub 2012-07-24
8217671 Parallel array architecture for constant current electro-migration stress testing Kanak B. Agarwal, Peter A. Habitz, Ying Liu, Deborah M. Massey, Alvin W. Strong 2012-07-10
8154309 Configurable PSRO structure for measuring frequency dependent capacitive loads Kanak B. Agarwal 2012-04-10
8120356 Measurement methodology and array structure for statistical stress and test of reliabilty structures Kanak B. Agarwal, Nazmul Habib, John G. Massey, Alvin W. Strong 2012-02-21
8089296 On-chip measurement of signals Kanak B. Agarwal 2012-01-03
7962874 Method and system for evaluating timing in an integrated circuit Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Anthony D. Polson 2011-06-14
7949482 Delay-based bias temperature instability recovery measurements for characterizing stress degradation and recovery Fadi H. Gebara, John P. Keane, Sani R. Nassif, Jeremy D. Schaub 2011-05-24
7868640 Array-based early threshold voltage recovery characterization measurement Kanak B. Agarwal, Nazmul Habib, John G. Massey, Alvin W. Strong 2011-01-11
7870525 Slack sensitivity to parameter variation based timing analysis Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey H. Oppold, Anthony D. Polson 2011-01-11
7865861 Method of generating wiring routes with matching delay in the presence of process variation Peter A. Habitz, David J. Hathaway, Anthony D. Polson 2011-01-04
7834649 Method and apparatus for statistical CMOS device characterization Kanak B. Agarwal, Ying Liu 2010-11-16
7823115 Method of generating wiring routes with matching delay in the presence of process variation Peter A. Habitz, David J. Hathaway, Anthony D. Polson 2010-10-26
7818137 Characterization circuit for fast determination of device capacitance variation Kanak B. Agarwal, Sani R. Nassif 2010-10-19
7782076 Method and apparatus for statistical CMOS device characterization Kanak B. Agarwal, Ying Liu 2010-08-24
7768814 Method and apparatus for measuring statistics of dram parameters with minimum perturbation to cell layout and environment Kanak B. Argawal 2010-08-03
7716616 Slack sensitivity to parameter variation based timing analysis Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey H. Oppold, Anthony D. Polson 2010-05-11
7680626 System and method of analyzing timing effects of spatial distribution in circuits David J. Hathaway, Anthony D. Polson 2010-03-16
7444608 Method and system for evaluating timing in an integrated circuit Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Anthony D. Polson 2008-10-28
7418689 Method of generating wiring routes with matching delay in the presence of process variation Peter A. Habitz, David J. Hathaway, Anthony D. Polson 2008-08-26
7401307 Slack sensitivity to parameter variation based timing analysis Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jeffrey H. Oppold, Anthony D. Polson 2008-07-15
7397259 Method and apparatus for statistical CMOS device characterization Kanak B. Agarwal, Ying Liu 2008-07-08
7302673 Method and system for performing shapes correction of a multi-cell reticle photomask design Peter A. Habitz, David J. Hathaway, Anthony D. Polson, Tad J. Wilder 2007-11-27