Issued Patents All Time
Showing 1–25 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11810832 | Heat sink configuration for multi-chip module | Janak G. Patel, Richard S. Graf, Manish Nayini | 2023-11-07 |
| 11682646 | IC chip package with dummy solder structure under corner, and related method | Manish Nayini, Richard S. Graf, Janak G. Patel | 2023-06-20 |
| 11171104 | IC chip package with dummy solder structure under corner, and related method | Manish Nayini, Richard S. Graf, Janak G. Patel | 2021-11-09 |
| 11054459 | Optimization of integrated circuit reliability | Carole D. Graas, Deborah M. Massey, John G. Massey, Pascal A. Nsame, Ernest Y. Wu +1 more | 2021-07-06 |
| 10996259 | Optimization of integrated circuit reliability | Carole D. Graas, Deborah M. Massey, John G. Massey, Pascal A. Nsame, Ernest Y. Wu +1 more | 2021-05-04 |
| 10989754 | Optimization of integrated circuit reliability | Carole D. Graas, Deborah M. Massey, John G. Massey, Pascal A. Nsame, Ernest Y. Wu +1 more | 2021-04-27 |
| 10794952 | Product performance test binning | Jeanne P. Bickford, Theodoros E. Anemikos, Susan K. Lichtensteiger | 2020-10-06 |
| 10700013 | IC wafer for identification of circuit dies after dicing | Wen Liu, Sebastian T. Ventrone, Adam C. Smith, Janice M. Adams | 2020-06-30 |
| 10564214 | Optimization of integrated circuit reliability | Carole D. Graas, Deborah M. Massey, John G. Massey, Pascal A. Nsame, Ernest Y. Wu +1 more | 2020-02-18 |
| 10539611 | Integrated circuit chip reliability qualification using a sample-specific expected fail rate | Jeanne P. Bickford, Baozhen Li, Tad J. Wilder | 2020-01-21 |
| 10216870 | Methodology to prevent metal lines from current pulse damage | Jeanne P. Bickford, Baozhen Li, Tad J. Wilder | 2019-02-26 |
| 10168685 | Application of stress conditions for homogenization of stress samples in semiconductor product acceleration studies | Mark A. Burns, Douglas S. Dewey, Daniel Reinhardt | 2019-01-01 |
| 10162325 | Application of stress conditions for homogenization of stress samples in semiconductor product acceleration studies | Mark A. Burns, Douglas S. Dewey, Daniel Reinhardt | 2018-12-25 |
| 10089161 | System and method for managing semiconductor manufacturing defects | Jeanne P. Bickford, Baozhen Li, Pascal A. Nsame | 2018-10-02 |
| 10067184 | Product performance test binning | Theodoros E. Anemikos, Jeanne P. Bickford, Susan K. Lichtensteiger | 2018-09-04 |
| 9940430 | Burn-in power performance optimization | Jeanne P. Bickford, Baozhen Li, Tad J. Wilder | 2018-04-10 |
| 9891275 | Integrated circuit chip reliability qualification using a sample-specific expected fail rate | Jeanne P. Bickford, Baozhen Li, Tad J. Wilder | 2018-02-13 |
| 9880892 | System and method for managing semiconductor manufacturing defects | Jeanne P. Bickford, Baozhen Li, Pascal A. Nsame | 2018-01-30 |
| 9791502 | On-chip usable life depletion meter and associated method | Jeanne P. Bickford, Baozhen Li, Tad J. Wilder | 2017-10-17 |
| 9739824 | Optimization of integrated circuit reliability | Carole D. Graas, Deborah M. Massey, John G. Massey, Pascal A. Nsame, Ernest Y. Wu +1 more | 2017-08-22 |
| 9639645 | Integrated circuit chip reliability using reliability-optimized failure mechanism targeting | Jeanne P. Bickford, Baozhen Li, Tad J. Wilder | 2017-05-02 |
| 9625325 | System and method for identifying operating temperatures and modifying of integrated circuits | Jeanne P. Bickford, Baozhen Li, Tad J. Wilder | 2017-04-18 |
| 9618566 | Systems and methods to prevent incorporation of a used integrated circuit chip into a product | Jeanne P. Bickford, Baozhen Li, Tad J. Wilder | 2017-04-11 |
| 9594868 | Scaling voltages in relation to die location | Eric A. Foreman, Kerim Kalafala | 2017-03-14 |
| 9506977 | Application of stress conditions for homogenization of stress samples in semiconductor product acceleration studies | Mark A. Burns, Douglas S. Dewey, Daniel Reinhardt | 2016-11-29 |