Issued Patents All Time
Showing 25 most recent of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12199003 | Packaging stacked substrates and an integrated circuit die using a lid and a stiffening structure | Luke England, Huahung Kao, Ronen Sinai | 2025-01-14 |
| 11810832 | Heat sink configuration for multi-chip module | Janak G. Patel, Manish Nayini, Nazmul Habib | 2023-11-07 |
| 11682646 | IC chip package with dummy solder structure under corner, and related method | Manish Nayini, Janak G. Patel, Nazmul Habib | 2023-06-20 |
| 11366154 | Enabling of functional logic in IC using thermal sequence enabling test | Sebastian T. Ventrone, Ezra D. B. Hall, Jack R. Smith | 2022-06-21 |
| 11171104 | IC chip package with dummy solder structure under corner, and related method | Manish Nayini, Janak G. Patel, Nazmul Habib | 2021-11-09 |
| 10978416 | Dual bond pad structure for photonics | Jeffrey P. Gambino, Robert K. Leidy, Jeffrey C. Maling | 2021-04-13 |
| 10833038 | Dual bond pad structure for photonics | Jeffrey P. Gambino, Robert K. Leidy, Jeffrey C. Maling | 2020-11-10 |
| 10734346 | Method of manufacturing chip-on-chip structure comprising sinterted pillars | Jay F. Leonard, David J. West, Charles H. Wilson | 2020-08-04 |
| 10651135 | Tamper detection for a chip package | Ezra D. B. Hall, Faraydon Pakbaz, Sebastian T. Ventrone | 2020-05-12 |
| 10476227 | Dual bond pad structure for photonics | Jeffrey P. Gambino, Robert K. Leidy, Jeffrey C. Maling | 2019-11-12 |
| 10340241 | Chip-on-chip structure and methods of manufacture | Jay F. Leonard, David J. West, Charles H. Wilson | 2019-07-02 |
| 10304763 | Producing wafer level packaging using leadframe strip and related device | Sudeep Mandal, Kibby B. Horsford | 2019-05-28 |
| 10249590 | Stacked dies using one or more interposers | Sudeep Mandal, Sebastian T. Ventrone | 2019-04-02 |
| 10170224 | Low temperature fabrication of lateral thin film varistor | Jeffrey P. Gambino, Sudeep Mandal | 2019-01-01 |
| 10083891 | Memory having thermoelectric heat pump and related IC chip package and method | Sebastian T. Ventrone, Ezra D. B. Hall | 2018-09-25 |
| 10043962 | Thermoelectric cooling using through-silicon vias | Sudeep Mandal | 2018-08-07 |
| 9972606 | Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding | Sebastian T. Ventrone | 2018-05-15 |
| 9941458 | Integrated circuit cooling using embedded peltier micro-vias in substrate | Jeffrey P. Gambino, Sudeep Mandal | 2018-04-10 |
| 9913405 | Glass interposer with embedded thermoelectric devices | Jeffrey P. Gambino, Sudeep Mandal, David J. Russell | 2018-03-06 |
| 9892999 | Producing wafer level packaging using leadframe strip and related device | Sudeep Mandal, Kibby B. Horsford | 2018-02-13 |
| 9882369 | Multi-layer heat shrinkable tubular sleeve | David Pearce, Thomas Rohde, John David Stoker, Timothy Stephen Smith | 2018-01-30 |
| 9870851 | Low temperature fabrication of lateral thin film varistor | Jeffrey P. Gambino, Sudeep Mandal | 2018-01-16 |
| 9865674 | Low temperature fabrication of lateral thin film varistor | Jeffrey P. Gambino, Sudeep Mandal | 2018-01-09 |
| 9818653 | Semiconductor TSV device package to which other semiconductor device package can be later attached | David J. West | 2017-11-14 |
| 9754911 | IC structure with angled interconnect elements | David J. West, Charles H. Wilson | 2017-09-05 |