Issued Patents All Time
Showing 1–25 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10801137 | Glass cloth including attached fibers | Bruce J. Chamberlin, Scott B. King, Joseph Kuczynski | 2020-10-13 |
| 10685919 | Reduced-warpage laminate structure | Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, Peter Slota, Jr. +1 more | 2020-06-16 |
| 10492289 | Coating for limiting substrate damage due to discrete failure | Bruce J. Chamberlin, Scott B. King, Joseph Kuczynski | 2019-11-26 |
| 10470290 | Coating for limiting substrate damage due to discrete failure | Bruce J. Chamberlin, Scott B. King, Joseph Kuczynski | 2019-11-05 |
| 10342122 | Interface for limiting substrate damage due to discrete failure | Bruce J. Chamberlin, Scott B. King, Joseph Kuczynski | 2019-07-02 |
| 10276535 | Method of fabricating contacts of an electronic package structure to reduce solder interconnect stress | Anson J. Call, Vijayeshwar D. Khanna, Krishna R. Tunga | 2019-04-30 |
| 10276534 | Reduction of solder interconnect stress | Anson J. Call, Vijayeshwar D. Khanna, Krishna R. Tunga | 2019-04-30 |
| 10206278 | Interface for limiting substrate damage due to discrete failure | Bruce J. Chamberlain, Scott B. King, Joseph Kuczynski | 2019-02-12 |
| 10172243 | Printed circuit board and methods to enhance reliability | Bruce J. Chamberlin, Scott B. King, Joseph Kuczynski | 2019-01-01 |
| 10108753 | Laminate substrate thermal warpage prediction for designing a laminate substrate | Anson J. Call, Vijayeshwar D. Khanna, Krishna R. Tunga | 2018-10-23 |
| 10080283 | Interface for limiting substrate damage due to discrete failure | Bruce J. Chamberlin, Scott B. King, Joseph Kuczynski | 2018-09-18 |
| 9990707 | Image analysis methods for plated through hole reliability | Sarah K. Czaplewski, Scott B. King, Joseph Kuczynski | 2018-06-05 |
| 9913405 | Glass interposer with embedded thermoelectric devices | Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal | 2018-03-06 |
| 9865557 | Reduction of solder interconnect stress | Anson J. Call, Vijayeshwar D. Khanna, Krishna R. Tunga | 2018-01-09 |
| 9659131 | Copper feature design for warpage control of substrates | Edmund Blackshear, Anson J. Call, Vijayeshwar D. Khanna, Douglas O. Powell | 2017-05-23 |
| 9613915 | Reduced-warpage laminate structure | Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, Peter Slota, Jr. +1 more | 2017-04-04 |
| 9585257 | Method of forming a glass interposer with thermal vias | Jeffrey P. Gambino, Richard S. Graf, Sudeep Mandal | 2017-02-28 |
| 9563732 | In-plane copper imbalance for warpage prediction | Anson J. Call, Vijayeshwar D. Khanna, Krishna R. Tunga | 2017-02-07 |
| 9543255 | Reduced-warpage laminate structure | Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, Peter Slota, Jr. +1 more | 2017-01-10 |
| 9484239 | Sacrificial carrier dicing of semiconductor wafers | Richard S. Graf, Douglas O. Powell, David J. West | 2016-11-01 |
| 9478453 | Sacrificial carrier dicing of semiconductor wafers | Richard S. Graf, Douglas O. Powell, David J. West | 2016-10-25 |
| 9401336 | Dual layer stack for contact formation | Charles L. Arvin, Harry D. Cox, Brian M. Erwin, Sarah H. Knickerbocker, Karen P. McLaughlin | 2016-07-26 |
| 9142501 | Under ball metallurgy (UBM) for improved electromigration | Charles L. Arvin, Minhua Lu, Eric D. Perfecto, Wolfgang Sauter, Krystyna W. Semkow +1 more | 2015-09-22 |
| 9105535 | Copper feature design for warpage control of substrates | Edmund Blackshear, Anson J. Call, Vijayeshwar D. Khanna, Douglas O. Powell | 2015-08-11 |
| 9099458 | Construction of reliable stacked via in electronic substrates—vertical stiffness control method | Karan Kacker, Douglas O. Powell, David L. Questad, Sri M. Sri-Jayantha | 2015-08-04 |