Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10956649 | Semiconductor package metal shadowing checks | Francesco Preda, Paul R. Walling | 2021-03-23 |
| 10770385 | Connected plane stiffener within integrated circuit chip carrier | Brian W. Quinlan, Krishna R. Tunga | 2020-09-08 |
| 10706204 | Automated generation of surface-mount package design | Jean Audet, Alain Ayotte, Franklin M. Baez, Deana Cosmadelis, Jason L. Frankel +5 more | 2020-07-07 |
| 10607928 | Reduction of laminate failure in integrated circuit (IC) device carrier | Sushumna Iruvanti, Shidong Li, Brian W. Quinlan, Kamal K. Sikka, Rui Wang | 2020-03-31 |
| 10546096 | Semiconductor package via stack checking | Paul R. Walling | 2020-01-28 |
| 10483233 | Split ball grid array pad for multi-chip modules | Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble | 2019-11-19 |
| 10423752 | Semiconductor package metal shadowing checks | Francesco Preda, Paul R. Walling | 2019-09-24 |
| 10276535 | Method of fabricating contacts of an electronic package structure to reduce solder interconnect stress | Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga | 2019-04-30 |
| 10276534 | Reduction of solder interconnect stress | Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga | 2019-04-30 |
| 10108753 | Laminate substrate thermal warpage prediction for designing a laminate substrate | Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga | 2018-10-23 |
| 9865557 | Reduction of solder interconnect stress | Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga | 2018-01-09 |
| 9659131 | Copper feature design for warpage control of substrates | Edmund Blackshear, Vijayeshwar D. Khanna, Douglas O. Powell, David J. Russell | 2017-05-23 |
| 9633914 | Split ball grid array pad for multi-chip modules | Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble | 2017-04-25 |
| 9563732 | In-plane copper imbalance for warpage prediction | Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga | 2017-02-07 |
| 9105535 | Copper feature design for warpage control of substrates | Edmund Blackshear, Vijayeshwar D. Khanna, Douglas O. Powell, David J. Russell | 2015-08-11 |
| 7786579 | Apparatus for crack prevention in integrated circuit packages | Jean Audet, Steven P. Ostrander, Douglas O. Powell, Roger D. Weekly | 2010-08-31 |
| 6584684 | Method for assembling a carrier and a semiconductor device | Peter J. Brofman, Jeffrey T. Coffin, Kathleen A. Stalter | 2003-07-01 |
| 6333563 | Electrical interconnection package and method thereof | Raymond A. Jackson, Mark G. Courtney, Stephen A. DeLaurentis, Mukta S. Farooq, Shaji Farooq +3 more | 2001-12-25 |
| 6300164 | Structure, materials, and methods for socketable ball grid | Stephen A. DeLaurentis, Shaji Farooq, Sung Kwon Kang, Sampath Purushothaman, Kathleen A. Stalter | 2001-10-09 |
| 6297559 | Structure, materials, and applications of ball grid array interconnections | Stephen A. DeLaurentis, Shaji Farooq, Sung Kwon Kang, Sampath Purushothaman, Kathleen A. Stalter | 2001-10-02 |
| 6218629 | Module with metal-ion matrix induced dendrites for interconnection | Peter J. Brofman, Jeffrey T. Coffin, Kathleen A. Stalter | 2001-04-17 |
| 6120885 | Structure, materials, and methods for socketable ball grid | Stephen A. DeLaurentis, Shaji Farooq, Sung Kwon Kang, Sampath Purushothaman, Kathleen A. Stalter | 2000-09-19 |
| 6114450 | Aryl Cyanate and/or diepoxide and tetrahydropyranyl-protected hydroxymethylated phenolic or hydroxystyrene resin | Krishna G. Sachdev, Michael Berger, Frank Louis Pompeo Jr. | 2000-09-05 |
| 5955543 | Aryl cyanate and/or diepoxide and hydroxymethylated phenolic or hydroxystyrene resin | Krishna G. Sachdev, Michael Berger, Frank L. Pompeo | 1999-09-21 |
| 5930597 | Reworkable polymer chip encapsulant | Stephen L. Buchwalter, Sushumna Iruvanti, Stanley J. Jasne, Frank L. Pompeo, Paul A. Zucco +1 more | 1999-07-27 |