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Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module |
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Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module |
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Semiconductor package floating metal checks |
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Decoupling capacitor stiffener |
Charles L. Arvin, Brian W. Quinlan, Charles L. Reynolds, Krishna R. Tunga, Thomas Weiss |
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Automated generation of surface-mount package design |
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Semiconductor package floating metal checks |
Jean Audet, Jason L. Frankel, Paul R. Walling |
2019-09-24 |
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Selecting design points on parameter functions having first sum of constraint set and second sum of optimizing set to improve second sum within design constraints |
— |
2008-03-18 |
| 7176731 |
Variation tolerant charge leakage correction circuit for phase locked loops |
David William Boerstler, Eskinder Hailu, Kazuhiko Miki |
2007-02-13 |
| 6958636 |
Charge leakage correction circuit for applications in PLLs |
David William Boerstler, Eskinder Hailu |
2005-10-25 |
| 6327552 |
Method and system for determining optimal delay allocation to datapath blocks based on area-delay and power-delay curves |
Mahadevamurty Nemani |
2001-12-04 |
