Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12111684 | Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module | Douglas J. Malone, Andreas H. A. Arp, Franklin M. Baez, Daniel M. Dreps, Chad Andrew Marquart +2 more | 2024-10-08 |
| 11775004 | Phase aligning and calibrating clocks from one phase lock loop (PLL) for a two-chip die module | Douglas J. Malone, Andreas H. A. Arp, Franklin M. Baez, Daniel M. Dreps, Chad Andrew Marquart +2 more | 2023-10-03 |
| 10949600 | Semiconductor package floating metal checks | Jean Audet, Franklin M. Baez, Paul R. Walling | 2021-03-16 |
| 10706204 | Automated generation of surface-mount package design | Jean Audet, Alain Ayotte, Franklin M. Baez, Anson J. Call, Deana Cosmadelis +5 more | 2020-07-07 |
| 10423751 | Semiconductor package floating metal checks | Jean Audet, Franklin M. Baez, Paul R. Walling | 2019-09-24 |
| 10375820 | Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures | Jinwoo Choi, Sungjun Chun, Paul R. Walling, Roger D. Weekly | 2019-08-06 |
| 9955567 | Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures | Jinwoo Choi, Sungjun Chun, Paul R. Walling, Roger D. Weekly | 2018-04-24 |
| 8927879 | Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures | Jinwoo Choi, Sungjun Chun, Paul R. Walling, Roger D. Weekly | 2015-01-06 |
| 7806341 | Structure for implementing secure multichip modules for encryption applications | Mukta G. Farooq, Benjamin V. Fasano, Harvey C. Hamel, Suresh D. Kadakia, David C. Long +2 more | 2010-10-05 |
| 7472836 | Method and structure for implementing secure multichip modules for encryption applications | Mukta G. Farooq, Benjamin V. Fasano, Harvey C. Hamel, Suresh D. Kadakia, David C. Long +2 more | 2009-01-06 |
| 7348667 | System and method for noise reduction in multi-layer ceramic packages | Sungjun Chun, Anand Haridass, Erich Klink, Brian L. Singletary | 2008-03-25 |
| 7325213 | Nested design approach | Harsaran S. Bhatia, Marie Cole, Michael S. Cranmer, Eric V. Kline, Kenneth A. Papae +1 more | 2008-01-29 |
| 7281667 | Method and structure for implementing secure multichip modules for encryption applications | Mukta G. Farooq, Benjamin V. Fasano, Harvey C. Hamel, Suresh D. Kadakia, David C. Long +2 more | 2007-10-16 |
| 7096451 | Mesh plane generation and file storage | Alice L. Donaldson, John A. Ludwig, Kenneth A. Papae, Rafael Perez-Acevedo, C. Timothy Ryan +1 more | 2006-08-22 |
| 6974722 | Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules | Glenn G. Daves, William F. Shutler, Anthony Wayne Sigler, Herbert I. Stoller, John Vetrero +1 more | 2005-12-13 |
| 6762489 | Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules | Glenn G. Daves, William F. Shutler, Anthony Wayne Sigler, Herbert I. Stoller, John Vetrero +1 more | 2004-07-13 |
| 5946552 | Universal cost reduced substrate structure method and apparatus | Kenneth A. Bird, Myra Muth Boenke, Sarah H. Knickerbocker, Ahmed Sayeed Shah | 1999-08-31 |
| 5831810 | Electronic component package with decoupling capacitors completely within die receiving cavity of substrate | Kenneth A. Bird, Peter J. Brofman, Francis F. Cappo, Suresh D. Kadakia, Sarah H. Knickerbocker +1 more | 1998-11-03 |