Issued Patents All Time
Showing 25 most recent of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12266598 | Dense via pitch interconnect to increase wiring density | Francesco Preda, Jose A. Hejase, Junyan Tang, Pavel Roy Paladhi, Nam H. Pham +2 more | 2025-04-01 |
| 11658378 | Vertically transitioning between substrate integrated waveguides (SIWs) within a multilayered printed circuit board (PCB) | Joshua C. Myers, Jose A. Hejase, Junyan Tang, Pavel Roy Paladhi, Wiren D. Becker +1 more | 2023-05-23 |
| 11399428 | PCB with substrate integrated waveguides using multi-band monopole antenna feeds for high speed communication | Pavel Roy Paladhi, Jose A. Hejase, Junyan Tang, Joshua C. Myers, Wiren D. Becker +1 more | 2022-07-26 |
| 10657308 | Signal via positioning in a multi-layer circuit board | Matteo Cocchini, Michael A. Cracraft | 2020-05-19 |
| 10375820 | Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures | Jinwoo Choi, Jason L. Frankel, Paul R. Walling, Roger D. Weekly | 2019-08-06 |
| 10223490 | Signal via positioning in a multi-layer circuit board using a genetic via placement solver | Matteo Cocchini, Michael A. Cracraft | 2019-03-05 |
| 10216884 | Signal via positioning in a multi-layer circuit board using a genetic via placement solver | Matteo Cocchini, Michael A. Cracraft | 2019-02-26 |
| 10135162 | Method for fabricating a hybrid land grid array connector | Jose A. Hejase, Wiren D. Becker, Daniel M. Dreps, Brian S. Beaman | 2018-11-20 |
| 10128593 | Connector having a body with a conductive layer common to top and bottom surfaces of the body as well as to wall surfaces of a plurality of holes in the body | Jose A. Hejase, Wiren D. Becker, Daniel M. Dreps, Brian S. Beaman | 2018-11-13 |
| 9980382 | Method of making a printed circuit board copper plane repair | Mahesh Bohra, Jesus Montanez, Daniel I. Rodriguez | 2018-05-22 |
| 9955567 | Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures | Jinwoo Choi, Jason L. Frankel, Paul R. Walling, Roger D. Weekly | 2018-04-24 |
| 9940426 | Signal via positioning in a multi-layer circuit board | Matteo Cocchini, Michael A. Cracraft | 2018-04-10 |
| 9916410 | Signal via positioning in a multi-layer circuit board | Matteo Cocchini, Michael A. Cracraft | 2018-03-13 |
| 9881115 | Signal via positioning in a multi-layer circuit board using a genetic via placement solver | Matteo Cocchini, Michael A. Cracraft | 2018-01-30 |
| 9875331 | Signal via positioning in a multi-layer circuit board using a genetic via placement solver | Matteo Cocchini, Michael A. Cracraft | 2018-01-23 |
| 9485866 | Printed circuit board copper plane repair | Mahesh Bohra, Jesus Montanez, Daniel I. Rodriguez | 2016-11-01 |
| 9477568 | Managing interconnect electromigration effects | Malcolm S. Allen-Ware, Jon A. Casey, Alan J. Drake, Charles R. Lefurgy, Karthick Rajamani +3 more | 2016-10-25 |
| 9374910 | Printed circuit board copper plane repair | Mahesh Bohra, Jesus Montanez, Daniel I. Rodriguez | 2016-06-21 |
| 9357649 | 276-pin buffered memory card with enhanced memory system interconnect | Brian J. Connolly | 2016-05-31 |
| 8962475 | Multi-layer circuit substrate fabrication method providing improved transmission line integrity and increased routing density | Anand Haridass, Roger D. Weekly | 2015-02-24 |
| 8927879 | Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures | Jinwoo Choi, Jason L. Frankel, Paul R. Walling, Roger D. Weekly | 2015-01-06 |
| 8813000 | System for designing substrates having reference plane voids with strip segments | Anand Haridass, Roger D. Weekly | 2014-08-19 |
| 8645889 | Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules | Jinwoo Choi, Anand Haridass, Roger D. Weekly | 2014-02-04 |
| 8638567 | Circuit manufacturing and design techniques for reference plane voids with strip segment | Anand Haridass, Roger D. Weekly | 2014-01-28 |
| 8624297 | Multi-layer circuit substrate fabrication and design methods providing improved transmission line integrity and increased routing density | Anand Haridass, Roger D. Weekly | 2014-01-07 |