Issued Patents All Time
Showing 26–37 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8625300 | Circuit manufacturing and design techniques for reference plane voids with strip segment | Anand Haridass, Roger D. Weekly | 2014-01-07 |
| 8407644 | Reducing crosstalk in the design of module nets | Dulce M. Altabella Cabrera, Anand Haridass, Tingdong Zhou | 2013-03-26 |
| 8325490 | Circuit manufacturing and design techniques for reference plane voids with strip segment | Anand Haridass, Roger D. Weekly | 2012-12-04 |
| 8288657 | Noise coupling reduction and impedance discontinuity control in high-speed ceramic modules | Jinwoo Choi, Anand Haridass, Roger D. Weekly | 2012-10-16 |
| 8257092 | Redundant clock channel for high reliability connectors | Daniel M. Dreps, Dierk Kaller, Rohan U. Mandrekar, Lei Shan | 2012-09-04 |
| 7945881 | Method of reducing crosstalk induced noise in circuitry designs | Anand Haridass, Jesus Montanez, Xiaomin Shen | 2011-05-17 |
| 7868608 | Detecting open ground connections in surface mount connectors | Anand Haridass, Jesus Montanez, Xiaomin Shen | 2011-01-11 |
| 7821796 | Reference plane voids with strip segment for improving transmission line integrity over vias | Anand Haridass, Roger D. Weekly | 2010-10-26 |
| 7646082 | Multi-layer circuit substrate and method having improved transmission line integrity and increased routing density | Anand Haridass, Roger D. Weekly | 2010-01-12 |
| 7348667 | System and method for noise reduction in multi-layer ceramic packages | Jason L. Frankel, Anand Haridass, Erich Klink, Brian L. Singletary | 2008-03-25 |
| 7313747 | Measuring microprocessor susceptibility to internal noise generation | Timothy M. Skergan, Ching-Lung Tong, Roger D. Weekly | 2007-12-25 |
| 6789241 | Methodology for determining the placement of decoupling capacitors in a power distribution system | Raymond E. Anderson, Larry D. Smith | 2004-09-07 |