Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12341089 | Device package substrate structure and method therefor | Chee Seng Foong, Trent S. Uehling | 2025-06-24 |
| 11798871 | Device package substrate structure and method therefor | Chee Seng Foong, Trent S. Uehling | 2023-10-24 |
| 11193953 | 3D chip testing through micro-C4 interface | Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani | 2021-12-07 |
| 10765002 | Electronic module power supply | Michael A. Christo, Julio A. Maldonado, Roger D. Weekly | 2020-09-01 |
| 10537019 | Substrate dielectric crack prevention using interleaved metal plane | Twila J. Eichman, Stanley Andrew Cejka, James S. Golab, Chee Seng Foong | 2020-01-14 |
| 10371717 | 3D chip testing through micro-C4 interface | Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani | 2019-08-06 |
| 10362674 | Electronic module power supply | Michael A. Christo, Julio A. Maldonado, Roger D. Weekly | 2019-07-23 |
| 10147654 | Package materials monitor and method therefor | Stanley Andrew Cejka | 2018-12-04 |
| 10080285 | Electronic module power supply | Michael A. Christo, Julio A. Maldonado, Roger D. Weekly | 2018-09-18 |
| 10037970 | Multiple interconnections between die | David Clegg, James S. Golab, Trent S. Uehling | 2018-07-31 |
| 9974174 | Package to board interconnect structure with built-in reference plane structure | Robert J. Wenzel, David Clegg | 2018-05-15 |
| 9972566 | Interconnect array pattern with a 3:1 signal-to-ground ratio | Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar | 2018-05-15 |
| 9726691 | 3D chip testing through micro-C4 interface | Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani | 2017-08-08 |
| 9646925 | Interconnect array pattern with a 3:1 signal-to-ground ratio | Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar | 2017-05-09 |
| 9600619 | Distribution of power vias in a multi-layer circuit board | Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar | 2017-03-21 |
| 9594865 | Distribution of power vias in a multi-layer circuit board | Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar | 2017-03-14 |
| 9543241 | Interconnect array pattern with a 3:1 signal-to-ground ratio | Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar | 2017-01-10 |
| 9456498 | Electronic module power supply | Michael A. Christo, Julio A. Maldonado, Roger D. Weekly | 2016-09-27 |
| 9146772 | Reducing power grid noise in a processor while minimizing performance loss | Lee Evan Eisen, Michael Stephen Floyd, Thomas Strach, Huajun Wen | 2015-09-29 |
| 9141421 | Reducing power grid noise in a processor while minimizing performance loss | Lee Evan Eisen, Michael Stephen Floyd, Thomas Strach, Huajun Wen | 2015-09-22 |
| 8683413 | Method for making high-speed ceramic modules with hybrid referencing scheme for improved performance and reduced cost | Wiren D. Becker, Jinwoo Choi | 2014-03-25 |
| 8572840 | Method of attaching an electronic module power supply | Michael A. Christo, Julio A. Maldonado, Roger D. Weekly | 2013-11-05 |
| 8407644 | Reducing crosstalk in the design of module nets | Dulce M. Altabella Cabrera, Sungjun Chun, Anand Haridass | 2013-03-26 |
| 8339803 | High-speed ceramic modules with hybrid referencing scheme for improved performance and reduced cost | Wiren D. Becker, Jinwoo Choi | 2012-12-25 |
| 8261226 | Network flow based module bottom surface metal pin assignment | Wiren D. Becker, Ruchir Puri, Haoxing Ren, Hua Xiang | 2012-09-04 |