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Trimmable banked capacitor |
Vidhya Ramachandran, Chonghua Zhong, Jun Zhai, Long Huang, Mengzhi Pang |
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Implementing high-speed signaling via dedicated printed circuit-board media |
Douglas A. Baska, Daniel M. Dreps, Roger D. Weekly |
2018-07-24 |
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Zhaoqing Chen, Matteo Cocchini, Tingdong Zhou |
2018-05-15 |
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Coreless multi-layer circuit substrate with minimized pad capacitance |
Kevin Bills, Mahesh Bohra, Jinwoo Choi, Tae Hong Kim |
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Interconnect array pattern with a 3:1 signal-to-ground ratio |
Zhaoqing Chen, Matteo Cocchini, Tingdong Zhou |
2017-05-09 |
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2017-03-21 |
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Distribution of power vias in a multi-layer circuit board |
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2017-03-14 |
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Interconnect array pattern with a 3:1 signal-to-ground ratio |
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John L. Colbert, Daniel M. Dreps, Paul M. Harvey |
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Packaging for eight-socket one-hop SMP topology |
John L. Colbert, Daniel M. Dreps, Paul M. Harvey |
2016-09-13 |
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Through-hole-vias in multi-layer printed circuit boards |
Moises Cases, Tae Hong Kim, Nusrat I. Sherali |
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High speed differential wiring in glass ceramic MCMS |
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Associating workflows with code sections in a document control system |
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Coreless multi-layer circuit substrate with minimized pad capacitance |
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Through-hole-vias in multi-layer printed circuit boards |
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2014-02-25 |
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Testing an optical fiber connection |
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Coreless multi-layer circuit substrate with minimized pad capacitance |
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Redundant clock channel for high reliability connectors |
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Through hole-vias in multi-layer printed circuit boards |
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2012-08-14 |
