Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12368137 | High bandwidth die to die interconnect with package area reduction | Jun Zhai, Kunzhong Hu | 2025-07-22 |
| 12283549 | High density interconnection using fanout interposer chiplet | Jun Zhai, Kunzhong Hu | 2025-04-22 |
| 11967528 | Structure and method for fabricating a computing system with an integrated voltage regulator module | Vidhya Ramachandran, Jun Zhai, Kunzhong Hu, Shawn Searles, Joseph T. DiBene, II +1 more | 2024-04-23 |
| 11670548 | Structure and method for fabricating a computing system with an integrated voltage regulator module | Vidhya Ramachandran, Jun Zhai, Kunzhong Hu, Shawn Searles, Joseph T. DiBene, II +1 more | 2023-06-06 |
| 11594494 | High density interconnection using fanout interposer chiplet | Jun Zhai, Kunzhong Hu | 2023-02-28 |
| 11587909 | High bandwidth die to die interconnect with package area reduction | Jun Zhai, Kunzhong Hu | 2023-02-21 |
| 11404337 | Scalable extreme large size substrate integration | Kunzhong Hu, Jiongxin Lu, Jun Zhai | 2022-08-02 |
| 11158621 | Double side mounted large MCM package with memory channel length reduction | Jun Zhai, Kunzhong Hu | 2021-10-26 |
| 11069665 | Trimmable banked capacitor | Vidhya Ramachandran, Jun Zhai, Long Huang, Mengzhi Pang, Rohan U. Mandrekar | 2021-07-20 |
| 10943869 | High density interconnection using fanout interposer chiplet | Jun Zhai, Kunzhong Hu | 2021-03-09 |
| 10818632 | Structure and method for fabricating a computing system with an integrated voltage regulator module | Vidhya Ramachandran, Jun Zhai, Kunzhong Hu, Shawn Searles, Joseph T. DiBene, II +1 more | 2020-10-27 |
| 10770433 | High bandwidth die to die interconnect with package area reduction | Jun Zhai, Kunzhong Hu | 2020-09-08 |
| 10685948 | Double side mounted large MCM package with memory channel length reduction | Jun Zhai, Kunzhong Hu | 2020-06-16 |
| 10181455 | 3D thin profile pre-stacking architecture using reconstitution method | Jun Zhai, Kunzhong Hu, Se Young Yang | 2019-01-15 |
| 10103138 | Dual-sided silicon integrated passive devices | Jun Zhai, Vidhya Ramachandran, Kunzhong Hu, Mengzhi Pang | 2018-10-16 |
| 9935076 | Structure and method for fabricating a computing system with an integrated voltage regulator module | Vidhya Ramachandran, Jun Zhai, Kunzhong Hu, Shawn Searles, Joseph T. DiBene, II +1 more | 2018-04-03 |
| 9748227 | Dual-sided silicon integrated passive devices | Jun Zhai, Vidhya Ramachandran, Kunzhong Hu, Mengzhi Pang | 2017-08-29 |
| 9659907 | Double side mounting memory integration in thin low warpage fanout package | Jun Zhai, Kunzhong Hu, Mengzhi Pang, Se Young Yang | 2017-05-23 |
| 9633974 | System in package fan out stacking architecture and process flow | Jun Zhai, Kunzhong Hu, Kwan-Yu Lai, Mengzhi Pang, Se Young Yang | 2017-04-25 |
| 9548288 | Integrated circuit die decoupling system with reduced inductance | Vidhya Ramachandran, Shawn Searles, Jun Zhai, Young Doo Jeon, Huabo Chen | 2017-01-17 |
| 9153530 | Thermal enhanced high density flip chip package | Kunzhong Hu | 2015-10-06 |
| 9118367 | Wideband power efficient high transmission power radio frequency (RF) transmitter | Ray (Ramon) Gomez, Leonard Dauphinee, Massimo Brandolini, Jianhong Xiao, Dongsoo Daniel Koh +2 more | 2015-08-25 |
| 8957694 | Wafer level package resistance monitor scheme | Kunzhong Hu, Edward Law | 2015-02-17 |
| 8945991 | Fabricating a wafer level semiconductor package having a pre-formed dielectric layer | Kevin Hu, Edward Law | 2015-02-03 |
| 8922014 | Wafer level semiconductor package | Kevin Hu, Edward Law | 2014-12-30 |